)]}'
{
  "commit": "c4e061572c9acd2915fa5f1dee10353db391e45a",
  "tree": "dbfd53ae50038eda11510eca6d0c653a2272f414",
  "parents": [
    "586ab96254fc5af6bb1a7bab0b0ad6cacf1dfe87"
  ],
  "author": {
    "name": "Kent McLeod",
    "email": "Kent.Mcleod@data61.csiro.au",
    "time": "Wed Nov 20 14:33:26 2019 +1100"
  },
  "committer": {
    "name": "Kent McLeod",
    "email": "Kent.Mcleod@data61.csiro.au",
    "time": "Wed Nov 20 14:51:09 2019 +1100"
  },
  "message": "trivial: Add missing register to list\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "57d0732a2203cbdad665e9d6c9542ffd22ccbd19",
      "old_mode": 33188,
      "old_path": "libsel4debug/sel4_arch_include/aarch64/sel4debug/sel4_arch/registers.h",
      "new_id": "8235d7d62cdee38b79a54cc67f8d5e3e382949d9",
      "new_mode": 33188,
      "new_path": "libsel4debug/sel4_arch_include/aarch64/sel4debug/sel4_arch/registers.h"
    }
  ]
}