tree a19445dbd26458decb185bb81575b78651027460
parent 72efa897a6c8abba8324d2cfedff5e64b5159dc8
author Yanyan Shen <Yanyan.Shen@data61.csiro.au> 1581320826 +1100
committer Siwei Zhuang <siwei.zhuang@data61.csiro.au> 1583384223 +1100

libsel4bench: Add support for RISC-V

Added initial support for RISC-V architecture.