)]}'
{
  "commit": "a6c966ae9e0e4439e01561aa5034db83bfeb6bd9",
  "tree": "a19445dbd26458decb185bb81575b78651027460",
  "parents": [
    "72efa897a6c8abba8324d2cfedff5e64b5159dc8"
  ],
  "author": {
    "name": "Yanyan Shen",
    "email": "Yanyan.Shen@data61.csiro.au",
    "time": "Mon Feb 10 18:47:06 2020 +1100"
  },
  "committer": {
    "name": "Siwei Zhuang",
    "email": "siwei.zhuang@data61.csiro.au",
    "time": "Thu Mar 05 15:57:03 2020 +1100"
  },
  "message": "libsel4bench: Add support for RISC-V\n\nAdded initial support for RISC-V architecture.\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "51cb7da760792d0a6a48ddab9fb7b865ee9b1193",
      "new_mode": 33188,
      "new_path": "libsel4bench/arch_include/riscv/sel4bench/arch/sel4bench.h"
    }
  ]
}