tree 32dd15a7968b71d983b63bdcfa39194a95d65608
parent a6c966ae9e0e4439e01561aa5034db83bfeb6bd9
author Siwei Zhuang <siwei.zhuang@data61.csiro.au> 1583383568 +1100
committer Siwei Zhuang <siwei.zhuang@data61.csiro.au> 1583901680 +1100

libsel4bench: Add event counter for riscv

Implement event counter, currently only supports sifive U540.