)]}'
{
  "commit": "8fbe6c089edc4f9cb02a6d31402055158bc2b6d8",
  "tree": "32dd15a7968b71d983b63bdcfa39194a95d65608",
  "parents": [
    "a6c966ae9e0e4439e01561aa5034db83bfeb6bd9"
  ],
  "author": {
    "name": "Siwei Zhuang",
    "email": "siwei.zhuang@data61.csiro.au",
    "time": "Thu Mar 05 15:46:08 2020 +1100"
  },
  "committer": {
    "name": "Siwei Zhuang",
    "email": "siwei.zhuang@data61.csiro.au",
    "time": "Wed Mar 11 15:41:20 2020 +1100"
  },
  "message": "libsel4bench: Add event counter for riscv\n\nImplement event counter, currently only supports sifive U540.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "51cb7da760792d0a6a48ddab9fb7b865ee9b1193",
      "old_mode": 33188,
      "old_path": "libsel4bench/arch_include/riscv/sel4bench/arch/sel4bench.h",
      "new_id": "61fe70b521678abf1216e078709ebd91ff914b4b",
      "new_mode": 33188,
      "new_path": "libsel4bench/arch_include/riscv/sel4bench/arch/sel4bench.h"
    }
  ]
}