tools/dts/nexus.dts

// DeviceTree for the Shodan SMC

/dts-v1/;

/ {
  #address-cells = <1>;
  #size-cells = <1>;
  compatible = "google,nexus0";
  model = "google,nexus0";

  chosen {
    // seL4 requires including devices that it should memory map here.
    seL4,kernel-devices =
        &{/soc/interrupt-controller@60000000};
    // (The timer is deliberately not here, since having more than one 4MB
    // range containing kernel devices causes an overflow beyond the end of
    // virtual address space when mapping them.)
  };

  cpus {
    #address-cells = <1>;
    #size-cells = <0>;
    cpu0: cpu@0 {
      device_type = "cpu";
      reg = <0>;
      compatible = "riscv";
      riscv,isa = "rv32imac";
      mmu-type = "riscv,sv39";
      status = "okay";

      cpu0_intc: interrupt-controller {
        #interrupt-cells = <1>;
        compatible = "riscv,cpu-intc";
        interrupt-controller;
        phandle = <0x0f>;
      };
    };
  };

  memory@50000000 {
    #address-cells = <1>;
    #size-cells = <1>;
    device_type = "memory";
    reg = <0x50000000 0x380000>;
  };

  soc {
    #address-cells = <1>;
    #size-cells = <1>;
    compatible = "simple-bus";
    ranges;
    timer@54010000 {
      compatible = "lowrisc,timer";
      clock-frequency = < 2500000 >;
      reg = < 0x54010000 0x1000 >;
      interrupt-parent = <&cpu0_intc>;
      interrupts = <5>;
      interrupts-extended = <&cpu0_intc 5>;
    };
    timersw@54011000 {
      compatible = "lowrisc,timer";
      clock-frequency = < 2500000 >;
      reg = < 0x54011000 0x1000 >;
      interrupt-parent = <&plic0>;
      interrupts = <38>;
      interrupts-extended = <&plic0 38>;
    };
    plic0: interrupt-controller@60000000 { // TOP_MATCHA_RV_PLIC_SMC_BASE_ADDR @ top_matcha.h
      #interrupt-cells = <1>;
      compatible = "riscv,plic0";
      reg = <0x60000000 0x8000000>; // TOP_MATCHA_RV_PLIC_SMC_SIZE_BYTES @ top_matcha.h
      interrupt-controller;
      interrupt-parent = <&cpu0_intc>;
      interrupts = <9>, <11>;
      interrupts-extended = <&cpu0_intc 9>, <&cpu0_intc 11>;
      riscv,ndev = <42>; // Must be >= kTopMatchaPlicIrqIdLastSmc @ top_matcha.h
      riscv,max-priority = <0x07>;
    };
    uart0: serial@54000000 {
      compatible = "lowrisc,uart";
      reg = <54000000 0x1000>;
      interrupt-parent = <&plic0>;
      interrupts = <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>;
      interrupts-extended = <&plic0 1>, <&plic0 2>, <&plic0 3>,
          <&plic0 4>, <&plic0 5>, <&plic0 6>, <&plic0 7>, <&plic0 8>;
    };
  };
};