[#60671] riscv: Rename PrivilegeArchitecture to PrivilegedArchitecture
diff --git a/platforms/cpus/andes_ae350_n25.repl b/platforms/cpus/andes_ae350_n25.repl
index 996d26c..fe1c7c0 100644
--- a/platforms/cpus/andes_ae350_n25.repl
+++ b/platforms/cpus/andes_ae350_n25.repl
@@ -9,7 +9,7 @@
cpuType: "rv32gc_xandes"
hartId: 0
timeProvider: empty
- privilegeArchitecture: PrivilegeArchitecture.Priv1_11
+ privilegedArchitecture: PrivilegedArchitecture.Priv1_11
plic: IRQControllers.PlatformLevelInterruptController @ sysbus 0xe4000000
numberOfSources: 1023
diff --git a/platforms/cpus/core-v-mcu.repl b/platforms/cpus/core-v-mcu.repl
index 6237bba..9407e4d 100644
--- a/platforms/cpus/core-v-mcu.repl
+++ b/platforms/cpus/core-v-mcu.repl
@@ -5,7 +5,7 @@
size: 0x80000
cpu: CPU.CV32E40P @ sysbus
- privilegeArchitecture: PrivilegeArchitecture.Priv1_11
+ privilegedArchitecture: PrivilegedArchitecture.Priv1_11
// We are overriding the default value to include information about coreID and clusterID
HartId: 0x3e0
diff --git a/platforms/cpus/kendryte_k210.repl b/platforms/cpus/kendryte_k210.repl
index 096b135..9bfb756 100644
--- a/platforms/cpus/kendryte_k210.repl
+++ b/platforms/cpus/kendryte_k210.repl
@@ -6,13 +6,13 @@
cpu1: CPU.RiscV64 @ sysbus
cpuType: "rv64imacfd_zicsr_zifencei"
- privilegeArchitecture: PrivilegeArchitecture.Priv1_10
+ privilegedArchitecture: PrivilegedArchitecture.Priv1_10
timeProvider: clint
hartId: 0
cpu2: CPU.RiscV64 @ sysbus
cpuType: "rv64imafdc_zicsr_zifencei"
- privilegeArchitecture: PrivilegeArchitecture.Priv1_10
+ privilegedArchitecture: PrivilegedArchitecture.Priv1_10
timeProvider: clint
hartId: 1
diff --git a/platforms/cpus/litex_linux_vexriscv_sdcard.repl b/platforms/cpus/litex_linux_vexriscv_sdcard.repl
index ef171ac..0c242c8 100644
--- a/platforms/cpus/litex_linux_vexriscv_sdcard.repl
+++ b/platforms/cpus/litex_linux_vexriscv_sdcard.repl
@@ -29,7 +29,7 @@
cpu: CPU.VexRiscv @ sysbus
cpuType: "rv32ima_zicsr_zifencei"
timeProvider: clint
- privilegeArchitecture: PrivilegeArchitecture.Priv1_10
+ privilegedArchitecture: PrivilegedArchitecture.Priv1_10
builtInIrqController: false
clint: IRQControllers.CoreLevelInterruptor @ sysbus 0xF0010000
diff --git a/platforms/cpus/litex_nexys_video_vexriscv_linux.repl b/platforms/cpus/litex_nexys_video_vexriscv_linux.repl
index 79ef372..8be348e 100644
--- a/platforms/cpus/litex_nexys_video_vexriscv_linux.repl
+++ b/platforms/cpus/litex_nexys_video_vexriscv_linux.repl
@@ -19,7 +19,7 @@
cpu: CPU.VexRiscv @ sysbus
cpuType: "rv32ima_zicsr_zifencei"
- privilegeArchitecture: PrivilegeArchitecture.Priv1_10
+ privilegedArchitecture: PrivilegedArchitecture.Priv1_10
timeProvider: clint
diff --git a/platforms/cpus/litex_tock.repl b/platforms/cpus/litex_tock.repl
index 6405334..e2ad316 100644
--- a/platforms/cpus/litex_tock.repl
+++ b/platforms/cpus/litex_tock.repl
@@ -38,7 +38,7 @@
cpu: CPU.VexRiscv @ sysbus
cpuType: "rv32imac_zicsr"
- privilegeArchitecture: PrivilegeArchitecture.Priv1_10
+ privilegedArchitecture: PrivilegedArchitecture.Priv1_10
timer0: Timers.LiteX_Timer_CSR32 @ sysbus 0x82002800
frequency: 100000000
diff --git a/platforms/cpus/litex_vexriscv_linux.repl b/platforms/cpus/litex_vexriscv_linux.repl
index beb4393..ae8cbc1 100644
--- a/platforms/cpus/litex_vexriscv_linux.repl
+++ b/platforms/cpus/litex_vexriscv_linux.repl
@@ -13,7 +13,7 @@
cpu: CPU.VexRiscv @ sysbus
timeProvider: cpu_timer
cpuType: "rv32ima_zicsr_zifencei"
- privilegeArchitecture: PrivilegeArchitecture.Priv1_10
+ privilegedArchitecture: PrivilegedArchitecture.Priv1_10
timer0: Timers.LiteX_Timer @ sysbus 0xF0001800
frequency: 100000000
diff --git a/platforms/cpus/litex_vexriscv_smp.repl b/platforms/cpus/litex_vexriscv_smp.repl
index 4ebc856..dbd1d5a 100644
--- a/platforms/cpus/litex_vexriscv_smp.repl
+++ b/platforms/cpus/litex_vexriscv_smp.repl
@@ -2,25 +2,25 @@
cpuType: "rv32ima_zicsr_zifencei"
hartId: 0
timeProvider: clint
- privilegeArchitecture: PrivilegeArchitecture.Priv1_10
+ privilegedArchitecture: PrivilegedArchitecture.Priv1_10
cpu_1: CPU.VexRiscv @ sysbus
cpuType: "rv32ima_zicsr_zifencei"
hartId: 1
timeProvider: clint
- privilegeArchitecture: PrivilegeArchitecture.Priv1_10
+ privilegedArchitecture: PrivilegedArchitecture.Priv1_10
cpu_2: CPU.VexRiscv @ sysbus
cpuType: "rv32ima_zicsr_zifencei"
hartId: 2
timeProvider: clint
- privilegeArchitecture: PrivilegeArchitecture.Priv1_10
+ privilegedArchitecture: PrivilegedArchitecture.Priv1_10
cpu_3: CPU.VexRiscv @ sysbus
cpuType: "rv32ima_zicsr_zifencei"
hartId: 3
timeProvider: clint
- privilegeArchitecture: PrivilegeArchitecture.Priv1_10
+ privilegedArchitecture: PrivilegedArchitecture.Priv1_10
ram: Memory.MappedMemory @ sysbus 0x40000000
size: 0x08000000
diff --git a/platforms/cpus/miv.repl b/platforms/cpus/miv.repl
index f84bbf1..4ed7465 100644
--- a/platforms/cpus/miv.repl
+++ b/platforms/cpus/miv.repl
@@ -15,7 +15,7 @@
cpu: CPU.RiscV32 @ sysbus
cpuType: "rv32imaf_zicsr_zifencei"
- privilegeArchitecture: PrivilegeArchitecture.Priv1_09
+ privilegedArchitecture: PrivilegedArchitecture.Priv1_09
timeProvider: clint
plic: IRQControllers.PlatformLevelInterruptController @ sysbus 0x40000000
diff --git a/platforms/cpus/miv_rv32.repl b/platforms/cpus/miv_rv32.repl
index dcdd87d..7f8c376 100644
--- a/platforms/cpus/miv_rv32.repl
+++ b/platforms/cpus/miv_rv32.repl
@@ -1,6 +1,6 @@
cpu: CPU.RiscV32 @ sysbus
cpuType: "rv32imc"
- privilegeArchitecture: PrivilegeArchitecture.Priv1_09
+ privilegedArchitecture: PrivilegedArchitecture.Priv1_09
timeProvider: clint
tcm: Memory.MappedMemory @ sysbus 0x40000000
diff --git a/platforms/cpus/polarfire-soc.repl b/platforms/cpus/polarfire-soc.repl
index fee2342..1c01929 100644
--- a/platforms/cpus/polarfire-soc.repl
+++ b/platforms/cpus/polarfire-soc.repl
@@ -1,7 +1,7 @@
e51: CPU.RiscV64 @ sysbus
cpuType: "rv64imac_zicsr_zifencei"
hartId: 0
- privilegeArchitecture: PrivilegeArchitecture.Priv1_10
+ privilegedArchitecture: PrivilegedArchitecture.Priv1_10
timeProvider: clint
CyclesPerInstruction: 8
init:
@@ -10,7 +10,7 @@
u54_1: CPU.RiscV64 @ sysbus
cpuType: "rv64gc_zicsr_zifencei"
hartId: 1
- privilegeArchitecture: PrivilegeArchitecture.Priv1_10
+ privilegedArchitecture: PrivilegedArchitecture.Priv1_10
timeProvider: clint
CyclesPerInstruction: 8
init:
@@ -19,7 +19,7 @@
u54_2: CPU.RiscV64 @ sysbus
cpuType: "rv64gc_zicsr_zifencei"
hartId: 2
- privilegeArchitecture: PrivilegeArchitecture.Priv1_10
+ privilegedArchitecture: PrivilegedArchitecture.Priv1_10
timeProvider: clint
CyclesPerInstruction: 8
init:
@@ -28,7 +28,7 @@
u54_3: CPU.RiscV64 @ sysbus
cpuType: "rv64gc_zicsr_zifencei"
hartId: 3
- privilegeArchitecture: PrivilegeArchitecture.Priv1_10
+ privilegedArchitecture: PrivilegedArchitecture.Priv1_10
timeProvider: clint
CyclesPerInstruction: 8
init:
@@ -37,7 +37,7 @@
u54_4: CPU.RiscV64 @ sysbus
cpuType: "rv64gc_zicsr_zifencei"
hartId: 4
- privilegeArchitecture: PrivilegeArchitecture.Priv1_10
+ privilegedArchitecture: PrivilegedArchitecture.Priv1_10
timeProvider: clint
CyclesPerInstruction: 8
init:
diff --git a/platforms/cpus/ri5cy.repl b/platforms/cpus/ri5cy.repl
index de11ed4..ea95473 100644
--- a/platforms/cpus/ri5cy.repl
+++ b/platforms/cpus/ri5cy.repl
@@ -18,4 +18,4 @@
lptmr2: UART.LowPower_Timer @ sysbus 0x4102B000
cpu: CPU.Ri5cy @ sysbus
- privilegeArchitecture: PrivilegeArchitecture.Priv1_10
+ privilegedArchitecture: PrivilegedArchitecture.Priv1_10
diff --git a/platforms/cpus/riscv_virt.repl b/platforms/cpus/riscv_virt.repl
index e01f9ef..9ca6bc9 100644
--- a/platforms/cpus/riscv_virt.repl
+++ b/platforms/cpus/riscv_virt.repl
@@ -6,7 +6,7 @@
cpu: CPU.RiscV32 @ sysbus
cpuType: "rv32imac"
- privilegeArchitecture: PrivilegeArchitecture.Priv1_10
+ privilegedArchitecture: PrivilegedArchitecture.Priv1_10
timeProvider: clint
hartId: 0
diff --git a/platforms/cpus/sifive-fe310.repl b/platforms/cpus/sifive-fe310.repl
index 80af600..cf87d6d 100644
--- a/platforms/cpus/sifive-fe310.repl
+++ b/platforms/cpus/sifive-fe310.repl
@@ -15,7 +15,7 @@
cpu: CPU.RiscV32 @ sysbus
cpuType: "rv32imac_zicsr_zifencei"
- privilegeArchitecture: PrivilegeArchitecture.Priv1_10
+ privilegedArchitecture: PrivilegedArchitecture.Priv1_10
timeProvider: clint
plic: IRQControllers.PlatformLevelInterruptController @ sysbus 0x0C000000
diff --git a/platforms/cpus/sifive-fu540.repl b/platforms/cpus/sifive-fu540.repl
index 2c99715..b0e5933 100644
--- a/platforms/cpus/sifive-fu540.repl
+++ b/platforms/cpus/sifive-fu540.repl
@@ -1,31 +1,31 @@
e51: CPU.RiscV64 @ sysbus
cpuType: "rv64imac_zicsr_zifencei"
hartId: 0
- privilegeArchitecture: PrivilegeArchitecture.Priv1_10
+ privilegedArchitecture: PrivilegedArchitecture.Priv1_10
timeProvider: clint
u54_1: CPU.RiscV64 @ sysbus
cpuType: "rv64gc_zicsr_zifencei"
hartId: 1
- privilegeArchitecture: PrivilegeArchitecture.Priv1_10
+ privilegedArchitecture: PrivilegedArchitecture.Priv1_10
timeProvider: clint
u54_2: CPU.RiscV64 @ sysbus
cpuType: "rv64gc_zicsr_zifencei"
hartId: 2
- privilegeArchitecture: PrivilegeArchitecture.Priv1_10
+ privilegedArchitecture: PrivilegedArchitecture.Priv1_10
timeProvider: clint
u54_3: CPU.RiscV64 @ sysbus
cpuType: "rv64gc_zicsr_zifencei"
hartId: 3
- privilegeArchitecture: PrivilegeArchitecture.Priv1_10
+ privilegedArchitecture: PrivilegedArchitecture.Priv1_10
timeProvider: clint
u54_4: CPU.RiscV64 @ sysbus
cpuType: "rv64gc_zicsr_zifencei"
hartId: 4
- privilegeArchitecture: PrivilegeArchitecture.Priv1_10
+ privilegedArchitecture: PrivilegedArchitecture.Priv1_10
timeProvider: clint
debug: Memory.MappedMemory @sysbus 0x0
diff --git a/platforms/cpus/sifive-fu740.repl b/platforms/cpus/sifive-fu740.repl
index ac67d2a..dde46a1 100644
--- a/platforms/cpus/sifive-fu740.repl
+++ b/platforms/cpus/sifive-fu740.repl
@@ -1,31 +1,31 @@
s7: CPU.RiscV64 @ sysbus
cpuType: "rv64imac_zicsr_zifencei"
hartId: 0
- privilegeArchitecture: PrivilegeArchitecture.Priv1_10
+ privilegedArchitecture: PrivilegedArchitecture.Priv1_10
timeProvider: clint
u74_1: CPU.RiscV64 @ sysbus
cpuType: "rv64gc_zicsr_zifencei"
hartId: 1
- privilegeArchitecture: PrivilegeArchitecture.Priv1_10
+ privilegedArchitecture: PrivilegedArchitecture.Priv1_10
timeProvider: clint
u74_2: CPU.RiscV64 @ sysbus
cpuType: "rv64gc_zicsr_zifencei"
hartId: 2
- privilegeArchitecture: PrivilegeArchitecture.Priv1_10
+ privilegedArchitecture: PrivilegedArchitecture.Priv1_10
timeProvider: clint
u74_3: CPU.RiscV64 @ sysbus
cpuType: "rv64gc_zicsr_zifencei"
hartId: 3
- privilegeArchitecture: PrivilegeArchitecture.Priv1_10
+ privilegedArchitecture: PrivilegedArchitecture.Priv1_10
timeProvider: clint
u74_4: CPU.RiscV64 @ sysbus
cpuType: "rv64gc_zicsr_zifencei"
hartId: 4
- privilegeArchitecture: PrivilegeArchitecture.Priv1_10
+ privilegedArchitecture: PrivilegedArchitecture.Priv1_10
timeProvider: clint
debug: Memory.MappedMemory @sysbus 0x0
diff --git a/platforms/cpus/starfive-jh7100.repl b/platforms/cpus/starfive-jh7100.repl
index fc918e3..5adaff3 100644
--- a/platforms/cpus/starfive-jh7100.repl
+++ b/platforms/cpus/starfive-jh7100.repl
@@ -1,13 +1,13 @@
U74_2: CPU.RiscV64 @ sysbus
cpuType: "rv64gc"
hartId: 1
- privilegeArchitecture: PrivilegeArchitecture.Priv1_10
+ privilegedArchitecture: PrivilegedArchitecture.Priv1_10
timeProvider: clint
U74_1: CPU.RiscV64 @ sysbus
cpuType: "rv64gc"
hartId: 0
- privilegeArchitecture: PrivilegeArchitecture.Priv1_10
+ privilegedArchitecture: PrivilegedArchitecture.Priv1_10
timeProvider: clint
dtim: Memory.MappedMemory @sysbus 0x0100000
diff --git a/platforms/cpus/verilated/riscv_verilated_uartlite.repl b/platforms/cpus/verilated/riscv_verilated_uartlite.repl
index 420ecac..ea4dbb6 100644
--- a/platforms/cpus/verilated/riscv_verilated_uartlite.repl
+++ b/platforms/cpus/verilated/riscv_verilated_uartlite.repl
@@ -1,6 +1,6 @@
cpu: CPU.RiscV32 @ sysbus
cpuType: "rv32g"
- privilegeArchitecture: PrivilegeArchitecture.Priv1_09
+ privilegedArchitecture: PrivilegedArchitecture.Priv1_09
timeProvider: clint
plic: IRQControllers.PlatformLevelInterruptController @ sysbus 0x40000000
diff --git a/src/Infrastructure b/src/Infrastructure
index 8db9a2a..5256986 160000
--- a/src/Infrastructure
+++ b/src/Infrastructure
@@ -1 +1 @@
-Subproject commit 8db9a2a1028f1be99f0c8a8417bd46a5cc2697a3
+Subproject commit 5256986af3799b0136e91af5d56908cb2fb84bc7
diff --git a/tests/peripherals/virtio-platform.repl b/tests/peripherals/virtio-platform.repl
index 611dfa1..cbe5021 100644
--- a/tests/peripherals/virtio-platform.repl
+++ b/tests/peripherals/virtio-platform.repl
@@ -23,7 +23,7 @@
cpu: CPU.VexRiscv @ sysbus
cpuType: "rv32imac_zicsr_zifencei"
builtInIrqController: false
- privilegeArchitecture: PrivilegeArchitecture.Priv1_10
+ privilegedArchitecture: PrivilegedArchitecture.Priv1_10
timeProvider: clint
ctrl: Miscellaneous.LiteX_SoC_Controller @ sysbus 0xf0000000
diff --git a/tests/platforms/LiteX/litex_linux_vexriscv.repl b/tests/platforms/LiteX/litex_linux_vexriscv.repl
index 5e771a7..5a92e97 100644
--- a/tests/platforms/LiteX/litex_linux_vexriscv.repl
+++ b/tests/platforms/LiteX/litex_linux_vexriscv.repl
@@ -55,7 +55,7 @@
cpu: CPU.VexRiscv @ sysbus
cpuType: "rv32ima_zicsr_zifencei"
- privilegeArchitecture: PrivilegeArchitecture.Priv1_10
+ privilegedArchitecture: PrivilegedArchitecture.Priv1_10
timeProvider: cpuTimer
led : Miscellaneous.LED @ gpio_out 0
diff --git a/tests/platforms/verilated/UARTLite.robot b/tests/platforms/verilated/UARTLite.robot
index ec024ad..21266bd 100644
--- a/tests/platforms/verilated/UARTLite.robot
+++ b/tests/platforms/verilated/UARTLite.robot
@@ -26,7 +26,7 @@
... """
... cpu: CPU.RiscV32 @ sysbus
... ${SPACE*4}cpuType: "rv32g"
-... ${SPACE*4}privilegeArchitecture: PrivilegeArchitecture.Priv1_09
+... ${SPACE*4}privilegedArchitecture: PrivilegedArchitecture.Priv1_09
... ${SPACE*4}timeProvider: clint
...
... plic: IRQControllers.PlatformLevelInterruptController @ sysbus 0x40000000
diff --git a/tests/unit-tests/per-core-registration.repl b/tests/unit-tests/per-core-registration.repl
index 61f2f32..2df573f 100644
--- a/tests/unit-tests/per-core-registration.repl
+++ b/tests/unit-tests/per-core-registration.repl
@@ -6,13 +6,13 @@
cpu1: CPU.RiscV64 @ sysbus
cpuType: "rv64imacfd_zicsr"
- privilegeArchitecture: PrivilegeArchitecture.Priv1_10
+ privilegedArchitecture: PrivilegedArchitecture.Priv1_10
timeProvider: empty
hartId: 0
cpu2: CPU.RiscV64 @ sysbus
cpuType: "rv64imafdc_zicsr"
- privilegeArchitecture: PrivilegeArchitecture.Priv1_10
+ privilegedArchitecture: PrivilegedArchitecture.Priv1_10
timeProvider: empty
hartId: 1
diff --git a/tests/unit-tests/pmp.robot b/tests/unit-tests/pmp.robot
index de2c63a..00e5b3b 100644
--- a/tests/unit-tests/pmp.robot
+++ b/tests/unit-tests/pmp.robot
@@ -5,7 +5,7 @@
... """
... cpu: CPU.RiscV32 @ sysbus
... ${SPACE*4}cpuType: "rv32gcv"
-... ${SPACE*4}privilegeArchitecture: PrivilegeArchitecture.Priv1_10
+... ${SPACE*4}privilegedArchitecture: PrivilegedArchitecture.Priv1_10
... ${SPACE*4}timeProvider: empty
...
... dram: Memory.MappedMemory @ sysbus 0x80000000
diff --git a/tests/unit-tests/riscv-interrupt-mode.robot b/tests/unit-tests/riscv-interrupt-mode.robot
index c0a1f6b..d9d8644 100644
--- a/tests/unit-tests/riscv-interrupt-mode.robot
+++ b/tests/unit-tests/riscv-interrupt-mode.robot
@@ -8,7 +8,7 @@
Execute Command using sysbus
Execute Command mach create
- Execute Command machine LoadPlatformDescriptionFromString "cpu: CPU.RiscV32 @ sysbus { cpuType: \\"rv32imac\\"; timeProvider: empty; privilegeArchitecture: PrivilegeArchitecture.Priv1_10; interruptMode: InterruptMode.${interruptMode} }"
+ Execute Command machine LoadPlatformDescriptionFromString "cpu: CPU.RiscV32 @ sysbus { cpuType: \\"rv32imac\\"; timeProvider: empty; privilegedArchitecture: PrivilegedArchitecture.Priv1_10; interruptMode: InterruptMode.${interruptMode} }"
Execute Command machine LoadPlatformDescriptionFromString "mem: Memory.MappedMemory @ sysbus 0x0 { size: 0x10000000 }"
Execute Command cpu TbCacheEnabled false