)]}' { "log": [ { "commit": "ac3e5af7921f493386282083614a3a89113d07f3", "tree": "c81085fbf6d3e788fc887384dbd068e01a63126b", "parents": [ "e4945117a114b6c7568686f91bae2f2f56addc0b" ], "author": { "name": "Pooja Hemashekar", "email": "hemashekar@roofline.ai", "time": "Wed Jul 22 19:04:31 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Jul 22 19:04:31 2026 +0200" }, "message": "[Codegen] Materialize encoding info for convolution with NCHWc layout (#24714)\n\nImplements convolution encoding materialization for data-tiled layouts.\n\nLayouts:\n- Input: [N, IC/c0, H, W, c0]\n- Filter: [OC/k0, IC/c0, FH, FW, c0, k0]\n- Output: [N, OC/k0, OH, OW, k0]\n\nwhere k0 and c0 are the inner tile sizes for the output and input\nchannels, respectively.\n\nScope:\n\n- Only 2D convolutions receive a data-tiled layout. \n- Grouped, depthwise, 1D, and 3D convolutions, and non-unit dilations,\nall materialize to the identity layout (existing un-tiled path, no\nbehavior change for these cases).\n - Arbitrary strides are supported.\n- Supports packed rank-5 input/output and rank-6 filter tensors. Rank-4\ninput/output is also accepted when `N\u003d1` batch dimension has been folded\nby upstream passes.\n- Currently supports fp32 convolutions only.\n\nSupported input forms:\n- nhwc_hwcf\n- nchw_fchw\n- nhwc_fhwc\n\nAll are materialized to the same packed NCHWc layout above.\n\nArchitecture-specific inner tiles:\n\n| Architecture | Condition | Inner tile (OC, IC) | Target ISA |\n\n|--------------|-------------------|---------------------|-----------------|\n| x86-64 | float, `+avx512f` | `{16,16}` | `VFMADD*` (zmm) |\n| arm64 | float | `{8,8}` | `FMLA` (NEON) |\n\nAll other configurations materialize to the identity layout.\n\nLayout motivation can be found here:\nhttps://hackmd.io/@phemashekar/conv-dt-layout\n\n---\n\nCo-authored-by: Jelle Schuhmacher \u003cschuehmacher@roofline.ai\u003e\nCo-authored-By: Claude Opus 4.8 (1M context) \u003cnoreply@anthropic.com\u003e\nSigned-off-by: Pooja Hemashekar \u003chemashekar@roofline.ai\u003e\n\n---------\n\nSigned-off-by: Pooja Hemashekar \u003chemashekar@roofline.ai\u003e\nCo-authored-by: Jelle Schuhmacher \u003cschuehmacher@roofline.ai\u003e\nCo-authored-by: Ege Beysel \u003cbeyselege@gmail.com\u003e" }, { "commit": "e4945117a114b6c7568686f91bae2f2f56addc0b", "tree": "1254c35df3c47dbdb8aaed5ce59c2325bc4a08d8", "parents": [ "bc908fd620d7378d1e2da0bff6ee70d77a965110" ], "author": { "name": "Kamil Karwacki", "email": "39648860+KamilKarwacki@users.noreply.github.com", "time": "Wed Jul 22 15:35:12 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Jul 22 15:35:12 2026 +0200" }, "message": "[LinalgExt][Attention] Specialize generics to matmuls (#24668)\n\nSpecialize generic matmul to named one in decompose-attention to prevent\nBubbleUpExpandShapes from propagating reshapes through contractions,\npreserving codegen-friendly structure for microkernels.\n\nSigned-off-by: Kamil Karwacki \u003ckarwacki@roofline.ai\u003e\nCo-authored-by: Thomas Ziereis \u003cziereis@roofline.ai\u003e" }, { "commit": "bc908fd620d7378d1e2da0bff6ee70d77a965110", "tree": "71a7b03495dca7b586d8a2bd8a7f56ced1cee637", "parents": [ "e53a335559976a31ed23225480a1baff823d2888" ], "author": { "name": "Zmicier Prybysh", "email": "zprybysh@baylibre.com", "time": "Wed Jul 22 14:07:17 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Jul 22 12:07:17 2026 +0000" }, "message": "[LLVMCPU][RISCV] Add RVV bf16 mmt4d ukernel using the Zvfbfwma widening MAC (bf16*bf16-\u003ef32) (#24695)\n\n## Summary\n\nOn RISC-V, a data-tiled bf16 matmul was computed by promoting LHS/RHS to\nf32, ignoring the `Zvfbfwma` bf16 widening multiply-accumulate extension\n(`vfwmaccbf16`) that LLVM already lowers to and that shipping silicon\nimplements. This PR adds a native `bf16 x bf16 -\u003e f32` `mmt4d`\nmicrokernel for RVV+`Zvfbfwma`. Naturally, this change is related to\n(and was implementing looking at) the existing f32, `int8` (#23734), and\nf16/`Zvfh` (#22231) ukernels.\n\n## How the change was tested\n\n1. Compiler e2e\nA `128x256 bf16 * 256x128 bf16 -\u003e 128x128 f32` matmul compiled for\n`riscv64 +v,+zvfbfwma` with `--iree-opt-data-tiling\n--iree-llvmcpu-enable-ukernels\u003dall`:\n Before: dispatch contains `arith.extf` f32-promotion, no ukernel.\nAfter: `Mmt4dTilingExpert` dispatch `matmul_128x128x256_bf16xbf16xf32`\nwith `iree_uk_mmt4d` + `iree_uk_pack`; **zero `arith.extf`**; all four\n`iree_uk_mmt4d_tile_bf16bf16f32_*_riscv_64_zvfbfwma` symbols present;\ngenerated RISC-V asm inner loop is `vfwmaccbf16.vf`.\n2. Numerics under `qemu-riscv64`\nA standalone harness calling the real tile functions matches an f32\nreference exactly. A control run without the extension crashes,\nconfirming `vfwmaccbf16` is genuinely executed. I used qemu 8.2 which\nexposes the extension as the experimental `-cpu max,x-zvfbfwma\u003dtrue`\nproperty.\n3. Tile selection under `qemu-riscv64`.\nVerified `iree_uk_mmt4d_select_tile_func_arch` (the\n`entry_point.c`/`tiles.inl` wiring) returns the correct bf16 tile for\neach M0 value when `cpu_data` has the `Zvfbfwma` bit, and does not\nselect it when the bit is clear — i.e. the feature is only enabled for\n`Zvfbfwma`.\n4. In-tree `mmt4d_test`.\nThe added case exercises the same path in CI\u0027s RISC-V cross-build (falls\nback to the generic tile if the CI toolchain can\u0027t assemble `Zvfbfwma`,\ni think it\u0027s the same limitation as `Zvfh` in #22303).\n\n### A note on CI coverage\n\nIf I understand correctly, the RISC-V CI job runs under an older\n`qemu-riscv64` on a stock `rv64gcv` profile that doesn\u0027t expose\n`Zvfbfwma`, and `mmt4d_test` *skips* (does not fail) any case whose\nfeature the runtime CPU lacks. Zvfbfwma is only assembled/executed on a\ntoolchain + qemu new enough to support it (qemu ≥ 8.2 exposes it as the\nexperimental `x-zvfbfwma` property). My point is: a green CI does not\nmean the bf16 kernel ran in CI — the functional validation of record is\nthe local `qemu-riscv64` 8.2 numerics + tile-selection runs described\nabove.\n\nDisclosure: this change was assisted by Claude Code, but the change was\nreviewed and thoroughly tested before being submitted.\n\n---------\n\nSigned-off-by: Zmicier Prybysh \u003czprybysh@baylibre.com\u003e" }, { "commit": "e53a335559976a31ed23225480a1baff823d2888", "tree": "7cde3dbce75573fe5e0b05102750d869d81fcb8a", "parents": [ "f9f4c9dbb4c17c766e8b83ee75cb05798ba6e808" ], "author": { "name": "Ege Beysel", "email": "beysel@roofline.ai", "time": "Tue Jul 21 17:44:31 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 21 15:44:31 2026 +0000" }, "message": "[LIT][LLVMCPU] fix failing rvv lowering strategy test (#24739)\n\nhttps://github.com/iree-org/iree/pull/24709 and\nhttps://github.com/iree-org/iree/pull/24601 merged one after the other,\nthe CI did not run again in-between on the merge base of the latter.\nThis adjusts the tile sizes selected according to the former.\n\nSigned-off-by: Ege Beysel \u003cbeyselege@gmail.com\u003e" }, { "commit": "f9f4c9dbb4c17c766e8b83ee75cb05798ba6e808", "tree": "a7f12cfd0e181c60daae3930d6b615fb061469c1", "parents": [ "adb29863b97067b1303714c920d0dcdf58e47135" ], "author": { "name": "Ege Beysel", "email": "beysel@roofline.ai", "time": "Tue Jul 21 16:00:42 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 21 16:00:42 2026 +0200" }, "message": "[Codegen][LLVMCPU] fix tile size selection for consumer unpack ops (#24709)\n\nIn the case of consumer pack operations, e.g. `mmt4d -\u003e unpack`\ndispatches, the tile sizes set for the unpack operation did not reflect\nunpacked destination dimension, but rather the outer source dimensions.\nThis PR fixes that. Correct tile sizes are necessary for vectorization\nand tile size alignment hints in case of scalable vectors.\n\nAlso, refactors the `(undo)scaleAndPermutateTilingForPack/UnpackOp`\nhelpers were a bit confusing, I switched `scaling` and `undoScaling` and\nintroduced a new helper method for code-sharing.\n\n---------\n\nSigned-off-by: Ege Beysel \u003cbeyselege@gmail.com\u003e" }, { "commit": "adb29863b97067b1303714c920d0dcdf58e47135", "tree": "b5ab5b48e48f929436ac456d6c15b8352f8938a0", "parents": [ "d02dcc6092e29cc607e350c25f9cb1e5b2eb7ea7" ], "author": { "name": "Ege Beysel", "email": "beysel@roofline.ai", "time": "Tue Jul 21 16:00:13 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 21 16:00:13 2026 +0200" }, "message": "[DT][CPU]: scalable tile size selection for RVV (#24601)\n\nEnables scalable tile size selection and propagation for RVV - as it is\nalready done for SVE.\n\nIn the SVE tests, there are more edge-cases with scalable tile sizes and\nthe behavior here is analogous to what we expect in RVV.\n\nSigned-off-by: Ege Beysel \u003cbeyselege@gmail.com\u003e" }, { "commit": "d02dcc6092e29cc607e350c25f9cb1e5b2eb7ea7", "tree": "c6dc59bead086a9f7bc9990a30a44d0e3d4201bb", "parents": [ "d56cb8083e3ed988a9b6586ed725d101a3682d91" ], "author": { "name": "Pan Zhang", "email": "98025960+zhangpan2001@users.noreply.github.com", "time": "Tue Jul 21 20:58:32 2026 +0800" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 21 14:58:32 2026 +0200" }, "message": "[CMake] Propagate WILL_FAIL through test rules (#24707)\n\nThis adds `WILL_FAIL` support to the CMake test wrappers that did not\nexpose it and forwards the value to the generated CTest entries.\n\nFor example, a backend-specific Python test for a known failing path can\nnow be declared directly:\n\n```cmake\niree_py_test(\n NAME\n known_failure_cuda\n SRCS\n \"known_failure_test.py\"\n ARGS\n \"--target_backend\u003dcuda\"\n \"--driver\u003dcuda\"\n WILL_FAIL\n TRUE\n)\n```\n\nIf the test exits with a non-zero status, CTest reports it as passing.\nIf it unexpectedly exits successfully, CTest reports a failure.\nPreviously, callers had to find the generated CTest name and set the\nproperty manually with `set_tests_properties`. Suite wrappers also pass\n`WILL_FAIL` to each test they generate.\n\nFixes: https://github.com/iree-org/iree/issues/13007\n\nAssisted-by: OpenAI\n\nSigned-off-by: zhangpan \u003c98025960+zhangpan2001@users.noreply.github.com\u003e" }, { "commit": "d56cb8083e3ed988a9b6586ed725d101a3682d91", "tree": "8a82760110ab42d577294db71bdfcfe85edd9628", "parents": [ "dc9601f88654749456c7cee4ae87e13de2654e1e" ], "author": { "name": "Maksymilian B. Knust", "email": "knust@roofline.ai", "time": "Tue Jul 21 14:41:09 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 21 14:41:09 2026 +0200" }, "message": "Integrate LLVM to llvm/llvm-project@ae7f0db2a0d6 (#24733)\n\nNo new things broken since the previous bump. Keeping existing reverts\nfor the following commits (not fixed upstream yet):\n\n - _[bazel] Correct config.h definitions for musl (#207295)_\n - _[AlwaysInliner] Do not inline on attribute mismatches_\n\nSigned-off-by: Maksymilian B. Knust \u003cknust@roofline.ai\u003e" }, { "commit": "dc9601f88654749456c7cee4ae87e13de2654e1e", "tree": "31945f1bcbc3b1740fef994e0041c2f5ff263823", "parents": [ "f2bcea10ee5782edc886119044a23acb79e6fba6" ], "author": { "name": "Eylon Eliyahu Krause", "email": "64223519+EylonKrause@users.noreply.github.com", "time": "Mon Jul 20 23:09:04 2026 +0300" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 20 22:09:04 2026 +0200" }, "message": "[LinalgExt] Fix WinogradInputTransformOp::verify incorrect dim-1 dynamic check (#24679)\n\n### Problem\n`WinogradInputTransformOp::verify` never validates the size of input\ndimension 1 for rank-2 inputs.\n\n### Root cause\n```cpp\nif ((!inputType.isDynamicDim(0) \u0026\u0026\n inputType.getDimSize(0) \u003e getInputTileSize()) ||\n (inputType.isDynamicDim(1) \u0026\u0026 // \u003c-- missing `!`\n inputType.getDimSize(1) \u003e getInputTileSize())) {\n return op-\u003eemitOpError(\"expected input dims not greater than input tile \"\n \"size if input is of rank 2\");\n}\n```\nThe dim-0 clause guards with `!isDynamicDim(0)`, but the dim-1 clause is\nmissing the `!`, which makes it dead:\n- if dim 1 is **static**, `isDynamicDim(1)` is false, so the clause\nshort-circuits and the static size is never compared;\n- if dim 1 is **dynamic**, `getDimSize(1)` is `ShapedType::kDynamic`\n(`INT64_MIN`), and `INT64_MIN \u003e getInputTileSize()` (a small positive\ntile size) is always false.\n\nSo a rank-2 input whose static dim 1 exceeds the input tile size is\nsilently accepted, contradicting the op\u0027s own diagnostic (`expected\ninput dims not greater than input tile size if input is of rank 2`).\n`verifyCompatibleShape` a few lines below only constrains the output\nshape, so nothing else catches it.\n\n### Fix\nAdd the missing `!`, mirroring the dim-0 clause one line above.\n\n### Testing\nStatic reasoning only (no local build). I\u0027m happy to add a\n`--verify-diagnostics` case to `Dialect/LinalgExt/IR/test/invalid.mlir`,\nbut there is currently no rank-2 `winograd.input_transform` example\nin-tree to mirror, so I left the test out of this minimal one-character\nfix — glad to add one if you\u0027d like.\n\n---------\n\nSigned-off-by: Eylon Krause \u003ceylon1909@gmail.com\u003e" }, { "commit": "f2bcea10ee5782edc886119044a23acb79e6fba6", "tree": "c9f45d77192b698bca5d8724ac61969ad0057c7b", "parents": [ "e8ad3fa0b85956c9901f6d76a8f610d2de6af746" ], "author": { "name": "Eylon Eliyahu Krause", "email": "64223519+EylonKrause@users.noreply.github.com", "time": "Mon Jul 20 16:24:05 2026 +0300" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 20 15:24:05 2026 +0200" }, "message": "[Util] Fix 32-bit wrap of util.string.format placeholder-count check (#24685)\n\n## Summary\nCompute `util.string.format`\u0027s expected-operand count in 64-bit so a\nnear-`UINT_MAX` placeholder index cannot wrap the check and slip past\nverification into an out-of-bounds access.\n\n## Context\n`util.string.format` interpolates its operands into `{N}`-style\nplaceholders. Its verifier — and `StringFormatOp::fold` — determine how\nmany operands the op should have from the highest placeholder index in\nthe format string, computed as `maxArgIndex + 1`. `maxArgIndex` was a\n32-bit `unsigned`.\n\n## Problem\nA format string with an explicit placeholder index of `UINT_MAX` makes\n`maxArgIndex + 1` overflow to `0`, so the verifier expects `0` operands\nand accepts the op even though the placeholder references argument\n`4294967295`. `fold` (and the verifier\u0027s own indexing) then read\n`argStrings[4294967295]` on an empty list — an out-of-bounds read. For\nexample, before this change the following op passed verification:\n```mlir\n%0 \u003d util.string.format \"{4294967295}\"() : () -\u003e !util.buffer\n```\n\n## Fix\nCast `maxArgIndex` to `uint64_t` so `maxArgIndex + 1` no longer wraps; an\nout-of-range placeholder is now rejected at verification. The same\ncomputation exists in two copies of `parseFormatString` (the verifier in\n`UtilOps.cpp` and the folder in `UtilOpFolders.cpp`); both are updated.\n\n`string_format_index_overflow` in `op_verification.mlir` checks the op\nabove is now rejected with a diagnostic instead of passing verification.\n\n---\nDisclosure: this contribution was authored with an AI coding assistant\n(Claude) and reviewed before submission.\n\nSigned-off-by: Eylon Krause \u003ceylon1909@gmail.com\u003e" }, { "commit": "e8ad3fa0b85956c9901f6d76a8f610d2de6af746", "tree": "44c123c81fbae331ce94e0d48787f29b5fcff342", "parents": [ "b94a5a53488c55ba4f3c5bbf60efc4027166a33c" ], "author": { "name": "huang-me", "email": "56251429+huang-me@users.noreply.github.com", "time": "Mon Jul 20 20:56:30 2026 +0800" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 20 14:56:30 2026 +0200" }, "message": "Drop CodegenPipelineOptLevel and use llvm::OptimizationLevel (#24728)\n\nAfter LLVM integrate in #24713 , the `llvm::OptimizationLevel` is now a\nenum, so there\u0027s no need of `CodegenPipelineOptLevel` and mapping helper\nfunction.\n\nthis change removes them and fixes #24715\n\nSigned-off-by: huang-me \u003camos0107+git@gmail.com\u003e" }, { "commit": "b94a5a53488c55ba4f3c5bbf60efc4027166a33c", "tree": "ced5747caf13a2f07374297e0c3def27957a1da9", "parents": [ "4cf1a7cd7e5a15140c1e7679d784dd75923a2bc9" ], "author": { "name": "Ege Beysel", "email": "beysel@roofline.ai", "time": "Mon Jul 20 14:15:24 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 20 14:15:24 2026 +0200" }, "message": "[DT][CPU]: RVV scalable encoding materialization (#24600)\n\nThis PR introduces scalable data-tiled layout selection and\nmaterialization for RVV. Though since there exist microkernels for the\nRV64 backend with the V extension, previous mechanism to select these\ndata-tiled layouts _statically_ based on the `+zvl*b` flags is also\npreserved and the scalable data-tiled layout materialization is hidden\nbehind the flag scalable vectorization flag.\n\nThe exactl layout selection (the tile sizes) though is based on the same\nprinciples as the static one - fully utilize all 32 of the V registers.\nF16 tile sizes that underutilize the V registers in the static case (see\n[this discord\nthread](https://discord.com/channels/689900678990135345/1456679894812590326/1461764521403224209))).\n\n**NOTE**: the `+zvl*b` flags DO NOT give us the _exact_ values of VLEN\nthat the hardware implements but rather the minimum one, meaning that\nthe previous static mechanism can underutilize the vector registers and\nis not vector-length agnostic.\n\n---------\n\nSigned-off-by: Ege Beysel \u003cbeyselege@gmail.com\u003e" }, { "commit": "4cf1a7cd7e5a15140c1e7679d784dd75923a2bc9", "tree": "758fe6ecbd640f90e42d7567bef5ec687619aef9", "parents": [ "a869dc3c51071fe9942c59706ec193ca88395dc6" ], "author": { "name": "pstarkcdpr", "email": "paul.stark@cdprojektred.com", "time": "Mon Jul 20 04:59:29 2026 -0700" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 20 13:59:29 2026 +0200" }, "message": "[CPU] Vectorize parallel dims for non-AVX512 x86 matmul defaults (#24701)\n\nSee GitHub issue: https://github.com/iree-org/iree/issues/24700\n\n`getDefaultMatmulVectorSizes` used `{1, 1, vectorSize}` for non-AVX512\nx86, which vectorizes only the reduction (`K`) dim and leaves the\nparallel/output dims scalar. This forces a horizontal reduction per\noutput element and is dramatically slower for f32 matmul_like /\nbatch_matmul kernels compared to v3.5 (~2.4x end-to-end regression on an\naffected model; ~92x on an isolated `512x512x512` matmul at `x86-64-v3`,\n`-O1`). Mirror the AArch64/RISC-V defaults by register-blocking the\nmatmul with `{8, vectorSize, vectorSize}`, vectorizing both parallel\ndims (`M` unroll, `N` vector) in addition to `K`.\n\nNumerics are unchanged. As a side effect, dynamic-shape accumulating\nGEMMs may now hoist a couple of tiny fixed-size remainder scratch\nbuffers (`memref.alloca`) from register-blocked peeling; the accumulator\nstays in registers and is written directly to the destination (no heap\nalloc, no `linalg.generic` copy). The `pipeline_tests.mlir`\naccumulating-GEMM guard is relaxed to forbid only heap allocation, and\nthe `select_x86_64` expected configs are updated `([1, 1, 0] -\u003e [8, 4,\n0])`.\n\n---------\n\nSigned-off-by: Paul Stark \u003cpaul.stark@cdprojektred.com\u003e\nCo-authored-by: Claude Opus 4.8 \u003cnoreply@anthropic.com\u003e" }, { "commit": "a869dc3c51071fe9942c59706ec193ca88395dc6", "tree": "3d00e93c529ad1e11884167e6ed9e7b65fd75848", "parents": [ "9c7d2ae876b372b4b3304fec07e8f29df35979b1" ], "author": { "name": "juanigp", "email": "juanigpisula@gmail.com", "time": "Fri Jul 17 18:25:49 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Jul 17 18:25:49 2026 +0200" }, "message": "Integrate LLVM to llvm/llvm-project@4641f4879e47 (#24713)\n\nIntegrates LLVM from abbcebe652841d to 4641f4879e47\n\nIREE changes:\n- Adapted to llvm/llvm-project#209424, which changed\n`llvm::OptimizationLevel` from a class to an enum.\n- Changed `DispatchCreationOptions` in\ncompiler/src/iree/compiler/Pipelines/Options.h so that `optLevel` is\nexplicitly initialized to `llvm::OptimizationLevel::O2`. This was the\ndefault value of the old `llvm::OptimizationLevel` class.\n- As a side note `CodegenPipelineOptLevel` in\n‎compiler/src/iree/compiler/Codegen/Utils/CodegenOptions.h was intended\nas a bridge from the old llvm class. Now, that enum seems to duplicate\nthe new llvm enum, but I did not remove it.\n- Adapted to llvm/llvm-project#204707, which changed\nLLVM::FunctionEntryCountAttr while LLVMFuncOp::build in\nllvm-project/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp still expects\n`std::optional\u003cuint64_t\u003e`\n\nThe integrate caused the following failing tests, that got addressed\nwith the cherry-picked changes below\n```\n The following tests FAILED:\n 1750 - iree/tests/e2e/matmul/e2e_matmul_cpu_dt_uk_f16_f16_llvm-cpu_local-task_avx2 (SEGFAULT) cpu_features\u003davx2 driver\u003dlocal-task iree/tests/e2e/matmul noriscv nowasm\n 1756 - iree/tests/e2e/matmul/e2e_matmul_cpu_dt_uk_bf16_bf16_llvm-cpu_local-task_avx2 (SEGFAULT) cpu_features\u003davx2 driver\u003dlocal-task iree/tests/e2e/matmul noriscv nowasm\n 1812 - iree/tests/e2e/matmul/e2e_matmul_cpu_experimental_dt_uk_f16_f16_llvm-cpu_local-task_avx2 (SEGFAULT) cpu_features\u003davx2 driver\u003dlocal-task iree/tests/e2e/matmul noriscv nowasm\n 1818 - iree/tests/e2e/matmul/e2e_matmul_cpu_experimental_dt_uk_bf16_bf16_llvm-cpu_local-task_avx2 (SEGFAULT) cpu_features\u003davx2 driver\u003dlocal-task iree/tests/e2e/matmul noriscv nowasm\n``` \nAdditional LLVM fixups:\n- Cherry-picked https://github.com/llvm/llvm-project/pull/210303\n- Cherry-picked https://github.com/llvm/llvm-project/pull/209345\n\n---------\n\nSigned-off-by: Juan Pisula \u003cjuanigpisula@gmail.com\u003e" }, { "commit": "9c7d2ae876b372b4b3304fec07e8f29df35979b1", "tree": "a5955aebe3472ad11b665dcd23ba51edd06f4a63", "parents": [ "4b11e1da59b1303d497ebf2f0c49c4d4bb422188" ], "author": { "name": "Pooja Hemashekar", "email": "hemashekar@roofline.ai", "time": "Thu Jul 16 20:51:20 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Jul 16 20:51:20 2026 +0200" }, "message": "[DispatchCreation] Register enum literals for parsing data-tiling hint op types (#24711)\n\nThe CLI option that lists op families eligible for data-tiling\nannotation takes `EncodingOpType` enum values, but no `cl::values` were\nregistered for it. Hence, passing a keyword such as `convolution` on the\ncommand line to\n`--iree-dispatch-creation-experimental-set-data-tiling-ops` failed to\nparse. Register the literals (`matmul`, `scaled_matmul`, `convolution`)\nso the option is actually usable from `iree-compile`.\n\nSigned-off-by: Pooja Hemashekar \u003chemashekar@roofline.ai\u003e" }, { "commit": "4b11e1da59b1303d497ebf2f0c49c4d4bb422188", "tree": "6e8b6af4e054fddd0877b0b50591696a1e69272a", "parents": [ "dd3505291ac1dfa2c6d05f67cc5d72ae763a263a" ], "author": { "name": "Federico Bruzzone", "email": "federico.bruzzone.i@gmail.com", "time": "Thu Jul 16 18:02:54 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Jul 16 16:02:54 2026 +0000" }, "message": "[LLVMCPU] Add SME lowering-strategy tests for f64 and unsupported i8 matmuls (#24656)\n\n`getMatmulAArch64SMEVectorSizes` (within `KernelDispatch.cpp`) only had\ntest coverage for the f32 matmul case.\n\nThis PR add two tests:\n- `f64` which uses `[4]x[8]` SME tiles instead of the `[8]x[8]` used for\nf32.\n\nhttps://github.com/iree-org/iree/blob/50d0addfb49254e0b7b746959b360c79437281cc/compiler/src/iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp#L1465-L1471\n- `i8` which SME does not support\n\nhttps://github.com/iree-org/iree/blob/50d0addfb49254e0b7b746959b360c79437281cc/compiler/src/iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp#L1488-L1502\n\n_AI disclaimer_: I used `Claude:Sonnet5` to write the checks.\n\n---------\n\nSigned-off-by: Federico Bruzzone \u003cfederico.bruzzone.i@gmail.com\u003e\nCo-authored-by: Ege Beysel \u003cbeyselege@gmail.com\u003e" }, { "commit": "dd3505291ac1dfa2c6d05f67cc5d72ae763a263a", "tree": "01c1eb6e94e0b574051c8b91bc0f89fda1bc6654", "parents": [ "810db8e1bc6d001a5aa76584b38b3a6cb900ee24" ], "author": { "name": "Lekkala_Sravya-mcw", "email": "lekkala.sravya@multicorewareinc.com", "time": "Thu Jul 16 21:31:29 2026 +0530" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Jul 16 16:01:29 2026 +0000" }, "message": "[Stream] Deduplicate identical tensor import/export ops (#24655)\n\n- This PR Adds canonicalization patterns to deduplicate identical\nstream.tensor.import and stream.tensor.export operations\n\n- Added test coverage for deduplication, non-deduplication, and\nintermediate-operation scenarios.\n\n---------\n\nSigned-off-by: LekkalaSravya3 \u003clekkala.sravya@multicorewareinc.com\u003e" }, { "commit": "810db8e1bc6d001a5aa76584b38b3a6cb900ee24", "tree": "ee3d0b633caf2890f4859a9e55ed088a10a90060", "parents": [ "a73ba39f4d814b4c27f024e969afda5cd0ac5481" ], "author": { "name": "Eylon Eliyahu Krause", "email": "64223519+EylonKrause@users.noreply.github.com", "time": "Thu Jul 16 18:30:37 2026 +0300" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Jul 16 17:30:37 2026 +0200" }, "message": "[Stream] Bounds-check tied operand index in verifyTiedOperandEncodings (#24686)\n\n## Summary\nBounds-check the tied-operand index in `verifyTiedOperandEncodings` so\nan out-of-range `tied_operands` value is reported as a verification\nerror instead of indexing the operand-encodings array out of bounds.\n\n## Context\n`verifyTiedOperandEncodings` (used by tied stream ops such as\n`stream.tensor.dispatch`) walks each result\u0027s tied operand and compares\n`operandEncodings[operandIndex]` against the result encoding.\n`operandIndex` is derived from the op\u0027s `tied_operands` attribute.\n\n## Problem\nThe `tied_operands` value is not range-checked for this op before the\nencoding lookup, so an index beyond the operand count reads\n`operandEncodings` out of bounds. Such an index is reachable through the\ngeneric assembly form (which bypasses the op\u0027s custom-format checks) —\nfor example, a dispatch with a single operand encoding but a\n`tied_operands` entry pointing at operand 5:\n```mlir\n%0 \u003d \"stream.tensor.dispatch\"(...) {\n tied_operands \u003d array\u003ci64: 5\u003e, ...\n} : (...) -\u003e ...\n```\n`operandIndex` (5) then indexes the single-element `operandEncodings`\nout of bounds during verification.\n\n## Fix\nIf `operandIndex \u003e\u003d operandEncodings.size()`, emit a verification error\n(`tied operand index N is out of range of the M operand encoding(s)`)\ninstead of indexing out of bounds.\n\n---\nDisclosure: this contribution was authored with an AI coding assistant\n(Claude) and reviewed before submission.\n\n---------\n\nSigned-off-by: Eylon Krause \u003ceylon1909@gmail.com\u003e" }, { "commit": "a73ba39f4d814b4c27f024e969afda5cd0ac5481", "tree": "abf7f7ae53165feae7e9b7af9b3c4dc968ce6029", "parents": [ "5051d70ed3fc7313572b4b7991ac4095d3dcb8b8" ], "author": { "name": "juanigp", "email": "juanigpisula@gmail.com", "time": "Tue Jul 14 16:58:52 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 14 16:58:52 2026 +0200" }, "message": "Integrate LLVM to llvm/llvm-project@abbcebe65284 (#24704)\n\nIntegrates LLVM to llvm/llvm-project@abbcebe65284 . No additional\ndownstream LLVM fix commits were required.\n\nSigned-off-by: Juan Pisula \u003cjuanigpisula@gmail.com\u003e" }, { "commit": "5051d70ed3fc7313572b4b7991ac4095d3dcb8b8", "tree": "cb7a15b82a0c0a0c9bb7c2585d2687c4743f35ea", "parents": [ "0893eac771d532b7110f1f7581d3f4cd0b9172bf" ], "author": { "name": "Artem Gindinson", "email": "gindinson@roofline.ai", "time": "Tue Jul 14 15:51:14 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 14 15:51:14 2026 +0200" }, "message": "[CI] Split the welcome message workflow for issue/PR (#24705)\n\nThe initial implementation in commit ff836d7 causes both issue-greeter\nand pull-request-greeter steps to be attempted [0] on both PRs and\nissues. Avoid the confusion by splitting into dedicated workflows and\nretiring the initial \"GitHub Automation\".\n\n[0] https://github.com/iree-org/iree/actions/runs/29332508441\n\nSigned-off-by: Artem Gindinson \u003cgindinson@roofline.ai\u003e" }, { "commit": "0893eac771d532b7110f1f7581d3f4cd0b9172bf", "tree": "e3ee61c18c54a8031fdae62ae96a890c3067e106", "parents": [ "ff836d7962ea9164f92458efcc6753b34c5e9b6c" ], "author": { "name": "pstarkcdpr", "email": "paul.stark@cdprojektred.com", "time": "Tue Jul 14 01:17:43 2026 -0700" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 14 10:17:43 2026 +0200" }, "message": "Fix compile error when hoisting constants. (#24672)\n\nThe constant-expression hoisting pass (`HoistIntoGlobalsPass`) could\nhoist a const-expr defined *inside* a `flow.dispatch.region`, placing\nthe resulting `util.global.load` within the region. When the region is\nlater outlined into an isolated executable module the global is no\nlonger visible, producing an \"undefined global\" verification error.\n\nSkip any const-expr whose defining op is strictly nested inside a\n`flow.dispatch.region` / `flow.dispatch.workgroups`. Hoisting the\ndispatch op itself remains valid and is unaffected.\n\nFixes issue https://github.com/iree-org/iree/issues/24671\n\n---------\n\nSigned-off-by: Paul Stark \u003cpaul.stark@cdprojektred.com\u003e\nCo-authored-by: Claude Opus 4.8 (1M context) \u003cnoreply@anthropic.com\u003e" }, { "commit": "ff836d7962ea9164f92458efcc6753b34c5e9b6c", "tree": "720ace554322699a789d5ac0fe2386762d8229ef", "parents": [ "42ff6d7ab7cec3e704c8139889ca09a0bdc841ab" ], "author": { "name": "Artem Gindinson", "email": "gindinson@roofline.ai", "time": "Tue Jul 14 07:45:06 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 14 07:45:06 2026 +0200" }, "message": "[Docs][Github] Add initial automated first-time contributor message (#24702)\n\nThe aim is to provide common links \u0026 guidance for first-time PR or issue\ncreators, and to communicate our AI tool use policy. The initial\nautomation runs on pull requests and issues created by first-time\ncontributors.\n\nThis introduces an expectation for first-time contributors to\nacknowledge the project policies through an explicit comment.\n\nThe workflow setup and CLI menu has been assisted by Codex and fully\nreviewed. The implementation logic was further refined manually.\nNaturally, the messages are fully hand-written.\n\nAddresses #24697.\n\n---------\n\nSigned-off-by: Artem Gindinson \u003cgindinson@roofline.ai\u003e" }, { "commit": "42ff6d7ab7cec3e704c8139889ca09a0bdc841ab", "tree": "5b5310fe4c2e3b4c11737c74cdc8762955e61145", "parents": [ "d495a537360cdf48551a94dffe562ef97e3878fe" ], "author": { "name": "maxbartel", "email": "bartel@roofline.ai", "time": "Mon Jul 13 17:08:51 2026 +0100" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 13 16:08:51 2026 +0000" }, "message": "[CI] Decomission amd gpu runners (#24703)\n\nSince we don\u0027t have access to the AMDGPU runners, we cannot fix the\ncache issue. Therefore it is time to sunset them." }, { "commit": "d495a537360cdf48551a94dffe562ef97e3878fe", "tree": "6808d2cec9ac78effcf5a3ab702a9f1ceb2453eb", "parents": [ "934cccb0ae697796206de737eb66a141dedc4431" ], "author": { "name": "Artem Gindinson", "email": "gindinson@roofline.ai", "time": "Fri Jul 10 13:24:42 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Jul 10 13:24:42 2026 +0200" }, "message": "[Torch] Support explicit scale values from `tm_tensor.attention` (#24566)\n\nWith dynamically sized GQA, explicit scale settings show up in\nONNX/Torch models such as Qwen3. Consume scale values from TMTensor op\nwhen provided.\n\nDepends on llvm/torch-mlir#4593.\n\nSigned-off-by: Artem Gindinson \u003cgindinson@roofline.ai\u003e" }, { "commit": "934cccb0ae697796206de737eb66a141dedc4431", "tree": "7f5d466500b37ff213affc6bad72bdbf3a5381af", "parents": [ "774d7bfdfc07a85e6582201b4d72fd0bd10e8b21" ], "author": { "name": "Maksymilian B. Knust", "email": "knust@roofline.ai", "time": "Thu Jul 09 18:59:38 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Jul 09 18:59:38 2026 +0200" }, "message": "Integrate LLVM to llvm/llvm-project@c138fc9acfdd (#24699)\n\nReplaced `createMemCpy` with `memCpyFn`\n - see https://github.com/llvm/llvm-project/pull/206966\n\nReverted b8cc84591b6a9b314b1e486b0db643f9f399cf90\n - it broke the bazel build\n - see https://github.com/llvm/llvm-project/pull/207295\n\nSigned-off-by: Maksymilian B. Knust \u003cknust@roofline.ai\u003e" }, { "commit": "774d7bfdfc07a85e6582201b4d72fd0bd10e8b21", "tree": "3d04d12094cb0ad90f35bfc625decb3b6c9f1fe9", "parents": [ "6caa91743beb38c369d45f5ccf10f6bd5fc2fd57" ], "author": { "name": "Roberto Laudani", "email": "laudani@roofline.ai", "time": "Thu Jul 09 15:02:43 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Jul 09 15:02:43 2026 +0200" }, "message": "[GlobalOpt] Add pass to convert broadcast batch_matmul to matmul (#24670)\n\nWhen a `linalg.batch_matmul` multiplies a batched input by a weight that\nis the same for every batch, every batch slice runs the same matmul\nagainst the same weight. This pass rewrites that case into a single\n`linalg.matmul`.\n\nFor an input of shape `[B, M, K]` and a weight `[K, N]` broadcast to\n`[B, K, N]`, the pass:\n\n 1. collapses the input to `[B*M, K]` using tensor.collapse_shape\n 2. multiplies it by the `[K, N]` weight using linalg.matmul\n 3. expands the result back to `[B, M, N]` using tensor.expand_shape\n\nThis removes the broadcast and turns the batched contraction into a\nplain\nmatmul, which downstream passes can handle better.\n\n---------\n\nSigned-off-by: Roberto Laudani \u003claudani@roofline.ai\u003e\nCo-authored-by: ziereis \u003cziereis@roofline.ai\u003e" }, { "commit": "6caa91743beb38c369d45f5ccf10f6bd5fc2fd57", "tree": "2b0474da9f5fdb81b1543a8c683edbfb8781fa33", "parents": [ "39088ea2e5e895fa67b45d386c76bdf0a12eb054" ], "author": { "name": "Artem Gindinson", "email": "gindinson@roofline.ai", "time": "Thu Jul 09 13:11:37 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Jul 09 13:11:37 2026 +0200" }, "message": "Integrate Torch-MLIR to llvm/torch-mlir@1828c5053 (#24691)\n\nIntegrates Torch-MLIR via `iree-org/torch-mlir/sm-iree-integrates/torch-20260707` branch.\n\nIncludes a CMake fix for https://github.com/llvm/torch-mlir/commit/35010fc69.\nPromotes ONNX ops test case `test_convtranspose_output_shape` to an expected pass.\n\nOn top of the integrated upstream commit, the 3 latest fixes from\n`sm-iree-integrates/llvm-20260617` are carried over:\n\n\"Adaptions to llvm/llvm-project@75b7809248cc for integrating LLVM into\nIREE\" by @schuermans-roofline as commit ec8720b\n\"Adaptions to llvm/llvm-project@917117ceeebf for integrating LLVM into\nIREE\" by @schuermans-roofline as commit 67c8c41\n\"Bump LLVM to llvm/llvm-project@0f3ca6bb9ca5\" by @lialan as commit\nba9dad2\n\n---------\n\nSigned-off-by: Artem Gindinson \u003cgindinson@roofline.ai\u003e" }, { "commit": "39088ea2e5e895fa67b45d386c76bdf0a12eb054", "tree": "b1ba4bdde2d7a691cadcbfa57ed532288a093ed2", "parents": [ "4b23615964a55134cc9210a05fd9b909f9d6c34e" ], "author": { "name": "Krzysztof Drewniak", "email": "Krzysztof.Drewniak@amd.com", "time": "Tue Jul 07 15:49:05 2026 -0700" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 07 15:49:05 2026 -0700" }, "message": "[ROCDL] Set relaxed buffer OOB mode (#24692)\n\nRecent LLVM changes to ptr addrspace(7)/fat buffer lowering (LLVM PRs\nhttps://github.com/llvm/llvm-project/pull/134329 and\nhttps://github.com/llvm/llvm-project/pull/134734 ) mean that\nunderalligned loads from buffer pointers get devectorized unless\n\"relaxed mode\" is enabled. IREE already has mitigations for the issues\nthat this OOB mode handles, so we must enable relaxed mode to prevent\nsevere regressions as seen in #24690.\n\nSadly there\u0027s no test for this one as we don\u0027t currently have tests for\nthe module translation and this is a hotfix so I want to keep it\nminimal." }, { "commit": "4b23615964a55134cc9210a05fd9b909f9d6c34e", "tree": "1975c8da9ee40d301379fad2a09766dd9d568507", "parents": [ "823446210fe229bc2b5e2b343d94639af8baf1ae" ], "author": { "name": "z combinator", "email": "49233942+hsqStephenZhang@users.noreply.github.com", "time": "Tue Jul 07 16:53:24 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 07 14:53:24 2026 +0000" }, "message": "[Stream] Fix crash in ConvertSplatConstantsIntoSplats for dense_resource (#24683)\n\n## Description\n\nhttps://github.com/iree-org/iree/issues/24448 crashes because:\n\n1. the frontend generates `DenseResourceElementsAttr` instead of\n`SplatElementsAttr` for models, it satisfies `isSplat()` because the\n`isSplat` has a default implementation and the tensor\u0027s elements share\nthe same value(for batchnorm, the weight is 1.0, the mean is 0.0 by\ndefault)\n2. the subsequent code attempts to `dyn_cast` the attribute to\n`SplatElementsAttr` , which returns `nullptr` and causes a segfault upon\ndereference.\n\n## Solution\n\n1. restrict the initial cast to `DenseElementsAttr`. since\n`DenseResourceElementsAttr` does not inherit from `DenseElementsAttr`,\nthe cast will safely fail and we could return `failure()` as expected.\n2. retrieve the splat value directly via\n`DenseElementsAttr::getSplatValue()` , which is natively supported for\nall splat-valued dense attributes\n\n## E2E test\n\nrun\nhttps://gist.github.com/hsqStephenZhang/31c9516a5b8788e7036061aae0ff46ba\n\nbefore the fix, it leads to segfault. after the fix, it exit\nsuccessfully.\n\n---------\n\nSigned-off-by: hsqStephenZhang \u003cstephenzhang666666@gmail.com\u003e\nCo-authored-by: Artem Gindinson \u003cgindinson@roofline.ai\u003e" }, { "commit": "823446210fe229bc2b5e2b343d94639af8baf1ae", "tree": "f1a5879c61a50458d35d8e6b22ed0689a288f447", "parents": [ "481c3c13931eb97cff5e89e8820871cc06574de2" ], "author": { "name": "Maksymilian B. Knust", "email": "maks@knust.one", "time": "Tue Jul 07 16:32:15 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 07 16:32:15 2026 +0200" }, "message": "Integrate LLVM to llvm/llvm-project@fcd02ae7caf2 (#24690)\n\nSigned-off-by: Maksymilian B. Knust \u003cknust@roofline.ai\u003e" }, { "commit": "481c3c13931eb97cff5e89e8820871cc06574de2", "tree": "c5f3edfc7d6f325910bdc1d5a4112aa1240853bf", "parents": [ "9080be216769444461f5f2c3a7d76a733a1e2e09" ], "author": { "name": "Federico Bruzzone", "email": "federico.bruzzone.i@gmail.com", "time": "Tue Jul 07 13:44:48 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jul 07 11:44:48 2026 +0000" }, "message": "[LLVMCPU] Fix ArmSME requiring classic SVE, breaking SME-only targets (e.g., Apple Silicon) (#24661)\n\n`enableAArch64SME` required `hasAnySVEFeature` in addition to\n`hasSMEFeature`, even though SME runs in Streaming SVE mode and does not\narchitecturally need classic (non-streaming) SVE. On SME-only targets\n(e.g. Apple Silicon, which implements `FEAT_SME`/`FEAT_SME2` but not\n`FEAT_SVE`), this meant:\n\n- **`+sme` alone**: `enableAArch64SME` was `false`, so the ArmSME\nlowering pipeline never ran. Vectorization silently fell back to scalar\ncode, but a leftover `vscale` was never inside a function marked\n\"streaming\", so it had no legal instruction-selection pattern:\n`iree-compile` crashed with `LLVM ERROR: Cannot select: vscale`.\n- **`+sve,+sme` together** (the only combination the existing SME e2e\ntests use): compiles fine, but a separate, Darwin-specific mechanism in\n`AArch64FrameLowering`/`AArch64PrologueEpilogue` is gated on `hasSVE()`.\nWith `+sve` set, LLVM emits `cntd` directly in the function prologue\n*before* `smstart`, which is illegal on hardware without non-streaming\nSVE and crashes at runtime with `SIGILL`.\n\nNeither combination worked; does that mean that, prior to this PR, it\nwasn\u0027t possible to use IREE\u0027s SME support on this class of hardware? If\nso, it implies that, until now, IREE couldn\u0027t leverage SME on Apple M4\nPro processors.\nBut I feel like I might be missing something...\n\nFixes #24660.\n\nSee: https://github.com/llvm/llvm-project/issues/204853\n\n\n@banach-space @egebeysel @AGindinson @maxbartel\n\n---------\n\nSigned-off-by: Federico Bruzzone \u003cfederico.bruzzone.i@gmail.com\u003e\nCo-authored-by: Ege Beysel \u003cbeyselege@gmail.com\u003e" }, { "commit": "9080be216769444461f5f2c3a7d76a733a1e2e09", "tree": "1174926d6dc880a95ebd445118bc0de58b9162a0", "parents": [ "a33484ef95581068c7d06c18279dcf8a389f889a" ], "author": { "name": "Akun", "email": "37210982+AkunCube@users.noreply.github.com", "time": "Mon Jul 06 21:46:58 2026 +0800" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 06 13:46:58 2026 +0000" }, "message": "[Flow][NFC] Optimize dispatch annotation type string generation (#24675)\n\nUse `getElementTypeOrSelf()` helper instead of manual ShapedType\nchecking\nand cache operand type strings to avoid repeated computation.\n\nThis simplifies the code and improves maintainability.\n\nSigned-off-by: cubehan3 \u003ccubehan3@gmail.com\u003e" }, { "commit": "a33484ef95581068c7d06c18279dcf8a389f889a", "tree": "299340831661d7f1cf8ac3243666584e25de897c", "parents": [ "78aff2f6bb768f60a4b468abf6737e11a10d4406" ], "author": { "name": "Eylon Eliyahu Krause", "email": "64223519+EylonKrause@users.noreply.github.com", "time": "Mon Jul 06 15:04:03 2026 +0300" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 06 14:04:03 2026 +0200" }, "message": "[Runtime] Honor the base argument in atoi_int32_base (#24677)\n\n### Problem\n`iree_string_view_atoi_int32_base` ignores its `base` argument.\n\n### Root cause\n`runtime/src/iree/base/string_view.c:387` calls `strtol(temp, \u0026end, 0)`\n— the `base` parameter is never used, so any requested radix is silently\ndiscarded and the string is parsed with C auto-detection (leading `0x` →\nhex, leading `0` → octal, else decimal). The three sibling `_base`\nfunctions forward the argument correctly: `strtoul(temp, \u0026end, base)`\n(uint32, :413), `strtoll(..., base)` (int64, :436), `strtoull(...,\nbase)` (uint64, :462). The non-`base` wrapper\n`iree_string_view_atoi_int32` already passes `0` explicitly (:399), so\nthe `_base` variant is clearly meant to honor a caller-supplied radix. A\ncaller requesting base 16 or 2 gets wrong values (e.g. base\u003d16 `\"10\"` →\n10 instead of 16).\n\n### Fix\nForward `base` to `strtol`, matching the sibling `_base` functions.\n\n### Verification\nStatic reasoning + sibling consistency; trivially checkable:\n`strtol(\"10\", \u0026e, 16) \u003d\u003d 16` vs the current `strtol(\"10\", \u0026e, 0) \u003d\u003d 10`.\n(No full runtime build on my machine — happy to add a unit test if\nuseful.)\n\nSigned-off-by: Eylon Krause \u003ceylon1909@gmail.com\u003e" }, { "commit": "78aff2f6bb768f60a4b468abf6737e11a10d4406", "tree": "ff07b030ac1c9e0a0aae0c2bc8ff06a5fef6d77d", "parents": [ "38afe0ad63d3d166671a4ed90da80e3a5b82a816" ], "author": { "name": "Christopher McGirr", "email": "mcgirr@roofline.ai", "time": "Mon Jul 06 11:49:56 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 06 09:49:56 2026 +0000" }, "message": "[InputConversion][TOSA]: change TOSA level to none (#24667)\n\nFor some TOSA lowering use-cases, we will have dynamic batch sizes and\nthis will trigger the level check. Here we set the level to none so that\ndynamic dimensions are allowed in TOSA IR.\n\nThe TOSA level check ensures that tensor sizes are within a certain\nthreshold but for our use-case with TFlite this is not always the case.\n\n---\n\nLIT tests created by Claude\n\n---------\n\nCo-authored-by: Artem Gindinson \u003cgindinson@roofline.ai\u003e" }, { "commit": "38afe0ad63d3d166671a4ed90da80e3a5b82a816", "tree": "b0e5944cbf537b88b33023a59b74638c33a3be9d", "parents": [ "21a674843cd24adfdd5d5e7acb1e91ee644b45e4" ], "author": { "name": "pstarkcdpr", "email": "paul.stark@cdprojektred.com", "time": "Mon Jul 06 02:22:58 2026 -0700" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jul 06 11:22:58 2026 +0200" }, "message": "Address crash in iree-reduce with complex tensors (#24674)\n\nSee issue https://github.com/iree-org/iree/issues/24673. Details are\nrepeated here.\n\n`iree-reduce` crashes in `reduceLinalgOnTensorsDelta` when it tries to\nreplace a `linalg` op that produces a **complex**-typed tensor. The\nstrategy builds a zero constant via `Builder::getZeroAttr(elementType)`,\nwhich returns a **null** attribute for `complex` (it only supports\nint/index/float). Creating an `arith.constant` from the null attribute\naborts the process.\n\nThe proposed fix simply does an early-out if the type is not int, float,\nor index instead of crashing.\n\nRepro:\n`interesting.sh`\n```bash\n#!/bin/bash\n# Interestingness oracle for iree-reduce.\n#\n# A reduced candidate is \"interesting\" (exit 0) only while it still contains the\n# complex-typed linalg.generic (identified by the complex.create in its body).\n# This keeps the reducer from deleting the op via an earlier strategy, so it\n# reaches reduceLinalgOnTensorsDelta with the complex op still present.\ngrep -q \"complex.create\" \"$1\"\n```\n\n`complex_repro.mlir`\n```\n// Minimal reproducer for the iree-reduce crash in reduceLinalgOnTensorsDelta.\n//\n// The linalg.generic writes a complex\u003cf32\u003e tensor. When the reducer decides to\n// replace this op with a linalg.fill of a zero constant, it calls\n// Builder::getZeroAttr(complex\u003cf32\u003e), which returns a null attribute. Building\n// an arith.constant from that null attribute crashes (\"Failed to infer result\n// type(s)\").\n//\n// The op survives the earlier reduction strategies because the interestingness\n// check (interesting.sh) requires \"complex.create\" to remain present, so the\n// reducer reaches reduceLinalgOnTensorsDelta with the complex op still in place.\nfunc.func @main(%arg0: tensor\u003c4xf32\u003e) -\u003e tensor\u003c4xcomplex\u003cf32\u003e\u003e {\n %empty \u003d tensor.empty() : tensor\u003c4xcomplex\u003cf32\u003e\u003e\n %0 \u003d linalg.generic {\n indexing_maps \u003d [affine_map\u003c(d0) -\u003e (d0)\u003e, affine_map\u003c(d0) -\u003e (d0)\u003e],\n iterator_types \u003d [\"parallel\"]\n } ins(%arg0 : tensor\u003c4xf32\u003e) outs(%empty : tensor\u003c4xcomplex\u003cf32\u003e\u003e) {\n ^bb0(%in: f32, %out: complex\u003cf32\u003e):\n %c \u003d complex.create %in, %in : complex\u003cf32\u003e\n linalg.yield %c : complex\u003cf32\u003e\n } -\u003e tensor\u003c4xcomplex\u003cf32\u003e\u003e\n return %0 : tensor\u003c4xcomplex\u003cf32\u003e\u003e\n}\n```\n\nRun using:\n```bash\nchmod +x interesting.sh\niree-reduce ./interesting.sh ./complex_repro.mlir -o reduced.mlir\n```\n\nCrashes with:\n```\nLLVM ERROR: Failed to infer result type(s):\n\"arith.constant\"(...) {} : () -\u003e ( ??? )\nPlease report issues to https://github.com/iree-org/iree/issues and include the crash backtrace.\nStack dump:\n0. Program arguments: ../../fix-undef-global-hoist/iree-compiler/tools/iree-reduce ./interesting.sh ./complex_repro.mlir -o reduced.mlir\n #0 0x00007aa82ee7cf5b llvm::sys::PrintStackTrace(llvm::raw_ostream\u0026, int) fix-undef-global-hoist/iree/third_party/llvm-project/llvm/lib/Support/Unix/Signals.inc:881:13\n #1 0x00007aa82ee7ab83 llvm::sys::RunSignalHandlers() fix-undef-global-hoist/iree/third_party/llvm-project/llvm/lib/Support/Signals.cpp:109:18\n #2 0x00007aa82ee7de71 SignalHandler(int, siginfo_t*, void*) fix-undef-global-hoist/iree/third_party/llvm-project/llvm/lib/Support/Unix/Signals.inc:448:38\n #3 0x00007aa828e45330 (/lib/x86_64-linux-gnu/libc.so.6+0x45330)\n #4 0x00007aa828e9eb2c __pthread_kill_implementation ./nptl/pthread_kill.c:44:76\n #5 0x00007aa828e9eb2c __pthread_kill_internal ./nptl/pthread_kill.c:78:10\n #6 0x00007aa828e9eb2c pthread_kill ./nptl/pthread_kill.c:89:10\n #7 0x00007aa828e4527e raise ./signal/../sysdeps/posix/raise.c:27:6\n #8 0x00007aa828e288ff abort ./stdlib/abort.c:81:7\n #9 0x00007aa82ee0850b llvm::report_fatal_error(llvm::Twine const\u0026, bool) fix-undef-global-hoist/iree/third_party/llvm-project/llvm/lib/Support/ErrorHandling.cpp:137:5\n#10 0x00007aa82ee0858e (fix-undef-global-hoist/iree-compiler/lib/libIREECompiler.so+0x580858e)\n#11 0x00007aa837dabc21 (fix-undef-global-hoist/iree-compiler/lib/libIREECompiler.so+0xe7abc21)\n#12 0x00007aa834c50cc1 llvm::SmallVectorTemplateCommon\u003cmlir::Type, void\u003e::begin() fix-undef-global-hoist/iree/third_party/llvm-project/llvm/include/llvm/ADT/SmallVector.h:276:45\n#13 0x00007aa834c50cc1 llvm::SmallVectorTemplateCommon\u003cmlir::Type, void\u003e::end() fix-undef-global-hoist/iree/third_party/llvm-project/llvm/include/llvm/ADT/SmallVector.h:278:27\n#14 0x00007aa834c50cc1 llvm::SmallVector\u003cmlir::Type, 2u\u003e::~SmallVector() fix-undef-global-hoist/iree/third_party/llvm-project/llvm/include/llvm/ADT/SmallVector.h:1242:46\n#15 0x00007aa834c50cc1 mlir::arith::ConstantOp::build(mlir::OpBuilder\u0026, mlir::OperationState\u0026, mlir::TypedAttr) fix-undef-global-hoist/iree-compiler/llvm-project/tools/mlir/include/mlir/Dialect/Arith/IR/ArithOps.cpp.inc:4379:1\n#16 0x00007aa834c131be mlir::arith::ConstantOp::create(mlir::OpBuilder\u0026, mlir::Location, mlir::TypedAttr) fix-undef-global-hoist/iree-compiler/llvm-project/tools/mlir/include/mlir/Dialect/Arith/IR/ArithOps.cpp.inc:4384:55\n#17 0x00007aa8337db6af mlir::Operation::getInlineOpResult(unsigned int) fix-undef-global-hoist/iree/third_party/llvm-project/mlir/include/mlir/IR/Operation.h:1035:61\n#18 0x00007aa8337db6af mlir::Operation::getOpResultImpl(unsigned int) fix-undef-global-hoist/iree/third_party/llvm-project/mlir/include/mlir/IR/Operation.h:1045:14\n#19 0x00007aa8337db6af mlir::Operation::getResult(unsigned int) fix-undef-global-hoist/iree/third_party/llvm-project/mlir/include/mlir/IR/Operation.h:432:54\n#20 0x00007aa8337db6af mlir::OpTrait::OneTypedResult\u003cmlir::Type\u003e::Impl\u003cmlir::arith::ConstantOp\u003e::getResult() fix-undef-global-hoist/iree/third_party/llvm-project/mlir/include/mlir/IR/OpDefinition.h:708:33\n#21 0x00007aa8337db6af mlir::OpTrait::OneTypedResult\u003cmlir::Type\u003e::Impl\u003cmlir::arith::ConstantOp\u003e::operator mlir::Value() fix-undef-global-hoist/iree/third_party/llvm-project/mlir/include/mlir/IR/OpDefinition.h:713:54\n#22 0x00007aa8337db6af mlir::iree_compiler::Reducer::reduceLinalgOnTensorsDelta(mlir::iree_compiler::Reducer::ChunkManager\u0026, mlir::iree_compiler::Reducer::WorkItem\u0026) fix-undef-global-hoist/iree/compiler/src/iree/compiler/Reducer/Strategies/ReduceLinalgOnTensorsDelta.cpp:114:18\n#23 0x00007aa834d464dd mlir::iree_compiler::Reducer::Delta::checkChunk(mlir::iree_compiler::Reducer::Chunk, llvm::function_ref\u003cvoid (mlir::iree_compiler::Reducer::ChunkManager\u0026, mlir::iree_compiler::Reducer::WorkItem\u0026)\u003e, llvm::ArrayRef\u003cmlir::iree_compiler::Reducer::Chunk\u003e, llvm::DenseSet\u003cmlir::iree_compiler::Reducer::Chunk, llvm::DenseMapInfo\u003cmlir::iree_compiler::Reducer::Chunk, void\u003e\u003e\u0026) fix-undef-global-hoist/iree/compiler/src/iree/compiler/Reducer/Framework/Delta.cpp:39:8\n#24 0x00007aa834d46aa7 llvm::LogicalResult::failed() const fix-undef-global-hoist/iree/third_party/llvm-project/llvm/include/llvm/Support/LogicalResult.h:43:43\n#25 0x00007aa834d46aa7 llvm::failed(llvm::LogicalResult) fix-undef-global-hoist/iree/third_party/llvm-project/llvm/include/llvm/Support/LogicalResult.h:71:58\n#26 0x00007aa834d46aa7 mlir::iree_compiler::Reducer::Delta::runDeltaPass(llvm::function_ref\u003cvoid (mlir::iree_compiler::Reducer::ChunkManager\u0026, mlir::iree_compiler::Reducer::WorkItem\u0026)\u003e, llvm::StringRef) fix-undef-global-hoist/iree/compiler/src/iree/compiler/Reducer/Framework/Delta.cpp:105:11\n#27 0x00007aa82f5d68ea mlir::iree_compiler::Reducer::ireeRunReducingStrategies(mlir::OwningOpRef\u003cmlir::Operation*\u003e, mlir::iree_compiler::Reducer::ReducerConfig\u0026) fix-undef-global-hoist/iree/compiler/src/iree/compiler/Reducer/iree_reduce_lib.cc:39:9\n#28 0x00007aa82edba149 ireeReduceMainFromCL(int, char**, mlir::MLIRContext\u0026) fix-undef-global-hoist/iree/compiler/src/iree/compiler/API/Internal/IREEReduceToolEntryPoint.cpp:102:26\n#29 0x00007aa82edba149 ireeReduceRunMain fix-undef-global-hoist/iree/compiler/src/iree/compiler/API/Internal/IREEReduceToolEntryPoint.cpp:134:7\n#30 0x00007aa828e2a1ca __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:74:3\n#31 0x00007aa828e2a28b call_init ./csu/../csu/libc-start.c:128:20\n#32 0x00007aa828e2a28b __libc_start_main ./csu/../csu/libc-start.c:347:5\n#33 0x00005a84cb2e26e5 _start (../../fix-undef-global-hoist/iree-compiler/tools/iree-reduce+0x16e5)\n```\n\nSigned-off-by: Paul Stark \u003cpaul.stark@cdprojektred.com\u003e\nCo-authored-by: Claude Opus 4.8 (1M context) \u003cnoreply@anthropic.com\u003e" }, { "commit": "21a674843cd24adfdd5d5e7acb1e91ee644b45e4", "tree": "8f2405e8a209c7fe97bb668cfbc7795972c6e185", "parents": [ "2ce6926916ed5095aa922a3cfd105f967139dd82" ], "author": { "name": "Tobias Fuchs", "email": "9053039+devtbi@users.noreply.github.com", "time": "Fri Jul 03 22:26:35 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Jul 03 20:26:35 2026 +0000" }, "message": "Integrate LLVM to llvm/llvm-project@bb315b7e2953 (#24666)\n\nCherry-picked https://github.com/iree-org/iree/pull/24634 (forward\nInnerTileAlignment overloads on IREE TilingInterface ops) for\nhttps://github.com/llvm/llvm-project/pull/204007.\n\nRegenerated CAPI exports\n\n---------\n\nSigned-off-by: Tobias Fuchs \u003cfuchs@roofline.ai\u003e\nCo-authored-by: Ege Beysel \u003cbeyselege@gmail.com\u003e\nCo-authored-by: Claude Opus 4.8 (1M context) \u003cnoreply@anthropic.com\u003e" }, { "commit": "2ce6926916ed5095aa922a3cfd105f967139dd82", "tree": "706588ae0f98a2e05a733b78c7348f2e19e0b80a", "parents": [ "aab676a1acbce65072607a0baae0dab739e0cc86" ], "author": { "name": "Benoit Jacob", "email": "jacob.benoit.1@gmail.com", "time": "Fri Jul 03 11:37:29 2026 -0400" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Jul 03 15:37:29 2026 +0000" }, "message": "[Codegen][CPU] Fill in the bf16 and i8 ukernel bodies + e2e tests. (#24572)\n\nReplaces the bf16 and i8-VNNI seeds\u0027 stub bodies with real SIMD\nimplementations, both generic over the `intrinsics_{m,n,k}` unrolling\nfactors and structured like the AMDGPU C ukernel they were adapted from\n(`iree_uk_amdgpu_multi_mma_mfma_i32_16x16x32_i8`): accumulators in\nregisters, an outer loop over the K tiles (`k_outer`), and inside it the\n`(intrinsics_m, intrinsics_n, intrinsics_k)` unroll. The `intrinsics_*`\narrive as constants at the inlined call site, so the loops fully unroll\nand the `acc_regs` arrays become fixed register files -- the bitcode-LTO\nequivalent of a C++ template, as the README describes.\n\n- bf16 (`MMA_X86_AVX512BF16_1x16x2_F32_BF16`): one `_mm512_dpbf16_ps`\nper (m, n, k), with the LHS K-pair broadcast via `set1_ps`.\n- i8 (`MMA_X86_AVX512VNNI_16x16x2_I32_I8_CASTI16`): the 16x16x2 tile is\nbit-compatible with the codegen path `lowerX86Avx512Vnni16x16x2I8` --\none `vpmovsxbw` widen of each i8 panel to i16, the `vpshufd` /\n`vbroadcasti32x4` fan-out, and 16 `vpdpwssd` over the block-interleaved\n(rlo, chi, rhi, clo) ACC layout. The i8 ukernel needs `-mavx512bw` for\nthe widen, so it is added to the VNNI copts.\n\n`LLVMCPUSelectUKernels` now only selects a ukernel when its bitcode\nactually exists (via `attachUKernelBitcodeOnOp`\u0027s bool return), so an\n`MMAIntrinsic` the cost model picks but for which no seed exists -- e.g.\nthe M\u003c-\u003eN-swapped `MMA_X86_AVX512BF16_16x1x2_F32_BF16` -- falls back to\ncodegen instead of dangling an undefined symbol.\n\nAdds two execution/numerical tests, the first of the new C-bitcode\nukernel path: `e2e_matmul_cpu_dt_inner_tiled_llvm_ukernel_bf16_f32`\n(avx512bf16) and `..._i8_i32` (avx512vnni). Each compiles a data-tiled\nmatmul with `--iree-llvmcpu-enable-llvm-ukernels\u003dinner_tiled`, links the\nukernel bitcode, runs on host and checks results against a reference --\nexercising the operand threading and generic `intrinsics_{m,n,k}`\nunrolling that the IR-level lit tests cannot. Both were confirmed to\nactually select their ukernel (not silently fall back to codegen).\n\nProgress towards https://github.com/iree-org/iree/issues/24574.\n\nSigned-off-by: Benoit Jacob \u003cjacob.benoit.1@gmail.com\u003e\nCo-authored-by: Claude Opus 4.8 (1M context) \u003cnoreply@anthropic.com\u003e" }, { "commit": "aab676a1acbce65072607a0baae0dab739e0cc86", "tree": "561ebfe6b17765c3df36a8a65fc3e1778707d815", "parents": [ "07d4cd57fa84f3851405d732ed617c91abce5d7f" ], "author": { "name": "Benoit Jacob", "email": "jacob.benoit.1@gmail.com", "time": "Fri Jul 03 11:05:12 2026 -0400" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Jul 03 11:05:12 2026 -0400" }, "message": "[NFC] Remove @bjacob from CODEOWNERS. (#24669)\n\nRemoves @bjacob as a code owner throughout the repo:\n\n- Drops the sole-owner `/tests/e2e @bjacob` rule entirely.\n- Removes `@bjacob` from `/compiler/src/iree/compiler/Dialect/Encoding/`\n\n🤖 Generated with [Claude Code](https://claude.com/claude-code)\n\nSigned-off-by: Benoit Jacob \u003cjacob.benoit.1@gmail.com\u003e" }, { "commit": "07d4cd57fa84f3851405d732ed617c91abce5d7f", "tree": "6ec6328a0fd537824b0f3b4ca2f78b5ea412ddf1", "parents": [ "1e4c8a80229b7d471a2d808d9e2e91f11b6da20f" ], "author": { "name": "Lekkala_Sravya-mcw", "email": "lekkala.sravya@multicorewareinc.com", "time": "Fri Jul 03 12:29:41 2026 +0530" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Jul 03 06:59:41 2026 +0000" }, "message": "[Flow] Fold chained tensor.slice ops (#24628)\n\nThis PR Adds a canonicalization pattern for `flow.tensor.slice` that\nfolds only when the producer of the slice source is also a\n`flow.tensor.slice`.\n\n**Example :**\n\n%producer \u003d flow.tensor.slice %src[producer_start for producer_length]\n%consumer \u003d flow.tensor.slice %producer[consumer_start for\nconsumer_length]\n\n**Canonicalizes to :**\n\n%consumer \u003d flow.tensor.slice %src[producer_start + consumer_start ] for\nconsumer_length\n\n---------\n\nSigned-off-by: LekkalaSravya3 \u003clekkala.sravya@multicorewareinc.com\u003e" }, { "commit": "1e4c8a80229b7d471a2d808d9e2e91f11b6da20f", "tree": "304a0edfdf5d1442c8504b74b4111301a747a2a8", "parents": [ "68206a1e511d0806dc46bd752a267fb15d0f2473" ], "author": { "name": "Stefan Schuermans", "email": "schuermans@roofline.ai", "time": "Thu Jul 02 19:58:49 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Jul 02 17:58:49 2026 +0000" }, "message": "[ROCM] Validate that target triple is set in module and test for it (#24663)\n\nSince LLVM commit\n00a6186128d3 AMDGPU: Prefer getting the triple from the module over the\nTargetMachine (#206055) the target riple of the module has to be set.\n\nThere was a suggestion for a dedicated test in\nhttps://github.com/iree-org/iree/pull/24662#discussion_r3512817954.\n\nAdd the check for the target triple to the ROCM module validation and\nadd a LIT test for it.\n\nThis change has been assisted by Claude Code. The changes have been\nreviewed manually before opening the PR.\n\nSigned-off-by: Stefan Schuermans \u003cschuermans@roofline.ai\u003e" }, { "commit": "68206a1e511d0806dc46bd752a267fb15d0f2473", "tree": "3e6ee3008c88db96879469628b8275f17c5a2cd7", "parents": [ "4d4e97d00f099a21f38eeff26f82a6d9e3643a11" ], "author": { "name": "Stefan Schuermans", "email": "schuermans@roofline.ai", "time": "Thu Jul 02 14:00:03 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Jul 02 14:00:03 2026 +0200" }, "message": "Integrate LLVM to llvm/llvm-project@9c51ed38f1e2 (#24662)\n\nAdapted compiler/src/iree/compiler/Codegen/Common/FoldTensorExtractOp.td\nto specify invariant argument to memref.load, required due to:\nf9f52bbcbc55 [mlir][memref] Add invariant attribute to memref.load\n(#206197)\n \nRe-generating the CAPI export files was required due to:\n9889e626983f [mlir-c] Add IRMapping C API bindings (#206146)\n\nSetting the module\u0027s targget triple in ROCM target due to:\n00a6186128d3 AMDGPU: Prefer getting the triple from the module over the\nTargetMachine (#206055)\n\nFinding the LLVM commits and adapting the IREE code has been assistend\nby Claude Code. The changes have been reviewed manually.\n\nSigned-off-by: Stefan Schuermans \u003cschuermans@roofline.ai\u003e" }, { "commit": "4d4e97d00f099a21f38eeff26f82a6d9e3643a11", "tree": "12e503276357c92e35a185b852e714c71170737a", "parents": [ "af08a7c817dbfafbd6872670e2c792d4732319f7" ], "author": { "name": "Yuwei Sun", "email": "49397791+YuWei-CH@users.noreply.github.com", "time": "Thu Jul 02 01:16:36 2026 -0700" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Jul 02 08:16:36 2026 +0000" }, "message": "[StableHLO] Guard convolution widen operand fusion (#24424)\n\nThe motivation for this PR is to keep StableHLO preprocessing valid for\nmixed-precision models that contain bf16/f32 convolutions. IREE\ncurrently folds widening converts into dense ops to reduce explicit\ncasts, but doing this for stablehlo.convolution can create invalid\noperand type combinations that StableHLO type inference rejects. This PR\navoid folding widening converts into stablehlo.convolution when doing so\nwould make the lhs and rhs element types invalid for StableHLO type\ninference.\n\n---------\n\nSigned-off-by: Hao Ren \u003crhao8608@gmail.com\u003e\nCo-authored-by: Hao Ren \u003crhao8608@gmail.com\u003e" }, { "commit": "af08a7c817dbfafbd6872670e2c792d4732319f7", "tree": "d4885d391a228601ed8e31a3c1fffc237a38e93a", "parents": [ "be57650d3723e4b8b44a341bd007fcb02062dd5b" ], "author": { "name": "juanigp", "email": "pisula@roofline.ai", "time": "Wed Jul 01 17:16:26 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Jul 01 15:16:26 2026 +0000" }, "message": "[DispatchCreation] Hoist scalar tensor.extract and tensor.extract_slice (#24552)\n\nThis PR aims to :\n- Enable hoisting tensor.extract ops that read from a scalar tensor\nalready outside the dispatch.\n- Loosen the requirement to hoist tensor.extract_slice ops.\n\n### Context\nI encountered this error when working on a modified version of LFM2.5. I\nattach a reproducer which captures the idea.\n\nA causal mask path stayed fused inside a QK matmul dispatch, which\nproduced large vectors due to tile size propagation in an mmt4d ukernel.\n\n```\nmask_slice_qk_repro.mlir:45:18: error: One or more operations with large vector sizes (32768 bytes) were found:\n\n\t%scores_3d \u003d torch.aten.bmm %q, %k : !torch.vtensor\u003c[16,?,64],f32\u003e, !torch.vtensor\u003c[16,64,256],f32\u003e -\u003e !torch.vtensor\u003c[16,?,256],f32\u003e\n ^\n\u003cunknown\u003e:0: note: %cst \u003d arith.constant dense\u003c0xFF800000\u003e : vector\u003c16x16x16x16xf32\u003e\n\n\u003cunknown\u003e:0: note: %cst_0 \u003d arith.constant dense\u003c0.000000e+00\u003e : vector\u003c16x16x16x16xf32\u003e\n\n\u003cunknown\u003e:0: note: %cst_1 \u003d arith.constant dense\u003c0\u003e : vector\u003c16x16x16x16xi8\u003e\n```\n\nThis originated due to the mask\u0027s slicing offset coming from a\ntensor.extract and subsequently producing a scalar metadata chain that\nremained inside the dispatch.\n\n### Proposed fix\n- `HoistUniformScalarComputePass` can accept more \"candidate ops\" than\njust arith ops. I just included tensor.extract since its what I ran\ninto. `isUniformScalarForDispatch` is still in charge to verify that the\ncandidate op is hoistable, so i added the logic to check the\ntensor.extract ops.\n- `IREE::Flow::isOffsetSizeAndStrideMappableToFlow` got split into two:\n`isOffsetSizeAndStrideStructurallyMappableToFlow` just checks if the\nslice can be represented as one flat contiguous byte range, and\n`isOffsetSizeAndStrideMappableToFlow` checks for that and the additional\ntensor.extract provenance.\n- `isHoistableOp` in HoistEncodingOps.cpp was rejecting extract slice\nops whose offset, size, and stride where produced by an extract op due\nto calling `isOffsetSizeAndStrideMappableToFlow` on them. Now it calls\n`isOffsetSizeAndStrideStructurallyMappableToFlow`.\n\n### Additional Notes:\n- I tried to not interfere with the codebase\u0027s original intentions.\n- Since the extract and extract_slice make it out of the dispatch, the\nlarge vectors never occur. I thought this was the right way to address\nthe root cause of the problem.\n- Inspecting the mmt4d ukernel tile size propagation, it seems that the\nproblematic large vectors originated due to propagating a pack op tiling\nconfig to the outer dims of an accumulator, which should not happen\nafaiu. I could work on that separate issue if it is of interest.\n\n\u003cdetails\u003e\n\u003csummary\u003emlir reproducer\u003c/summary\u003e\n\n```mlir\nmodule @module {\n func.func @forward(\n %query: !torch.vtensor\u003c[1,16,?,64],f32\u003e,\n %key: !torch.vtensor\u003c[1,16,64,256],f32\u003e,\n %mask: !torch.vtensor\u003c[256,256],ui8\u003e,\n %positions: !torch.vtensor\u003c[1],si64\u003e)\n -\u003e !torch.vtensor\u003c[1,16,?,256],f32\u003e\n attributes {torch.assume_strict_symbolic_shapes} {\n %s \u003d torch.symbolic_int \"s\" {min_val \u003d 1, max_val \u003d 256} : !torch.int\n torch.bind_symbolic_shape %query, [%s], affine_map\u003c()[s0] -\u003e (1, 16, s0, 64)\u003e : !torch.vtensor\u003c[1,16,?,64],f32\u003e\n\n %int0 \u003d torch.constant.int 0\n %int1 \u003d torch.constant.int 1\n %int2 \u003d torch.constant.int 2\n %int16 \u003d torch.constant.int 16\n %int64 \u003d torch.constant.int 64\n %int256 \u003d torch.constant.int 256\n %int-1 \u003d torch.constant.int -1\n\n %seq_len \u003d torch.aten.size.int %query, %int2 : !torch.vtensor\u003c[1,16,?,64],f32\u003e, !torch.int -\u003e !torch.int\n %pos_tensor \u003d torch.aten.select.int %positions, %int0, %int-1 : !torch.vtensor\u003c[1],si64\u003e, !torch.int, !torch.int -\u003e !torch.vtensor\u003c[],si64\u003e\n %pos \u003d torch.aten.item %pos_tensor : !torch.vtensor\u003c[],si64\u003e -\u003e !torch.int\n\n %end \u003d torch.aten.add.int %pos, %seq_len : !torch.int, !torch.int -\u003e !torch.int\n %bool_dtype \u003d torch.constant.int 11\n %mask_bool \u003d torch.prims.convert_element_type %mask, %bool_dtype : !torch.vtensor\u003c[256,256],ui8\u003e, !torch.int -\u003e !torch.vtensor\u003c[256,256],i1\u003e\n %mask_slice \u003d torch.aten.slice.Tensor %mask_bool, %int0, %pos, %end, %int1 : !torch.vtensor\u003c[256,256],i1\u003e, !torch.int, !torch.int, !torch.int, !torch.int -\u003e !torch.vtensor\u003c[?,256],i1\u003e\n torch.bind_symbolic_shape %mask_slice, [%s], affine_map\u003c()[s0] -\u003e (s0, 256)\u003e : !torch.vtensor\u003c[?,256],i1\u003e\n\n %float-Inf \u003d torch.constant.float 0xFFF0000000000000\n %float0 \u003d torch.constant.float 0.000000e+00\n %f32_dtype \u003d torch.constant.int 6\n %none \u003d torch.constant.none\n %cpu \u003d torch.constant.device \"cpu\"\n %neg_inf \u003d torch.aten.scalar_tensor %float-Inf, %f32_dtype, %none, %cpu, %none : !torch.float, !torch.int, !torch.none, !torch.Device, !torch.none -\u003e !torch.vtensor\u003c[],f32\u003e\n %mask_bias \u003d torch.aten.where.ScalarSelf %mask_slice, %float0, %neg_inf : !torch.vtensor\u003c[?,256],i1\u003e, !torch.float, !torch.vtensor\u003c[],f32\u003e -\u003e !torch.vtensor\u003c[?,256],f32\u003e\n torch.bind_symbolic_shape %mask_bias, [%s], affine_map\u003c()[s0] -\u003e (s0, 256)\u003e : !torch.vtensor\u003c[?,256],f32\u003e\n\n %q_shape \u003d torch.prim.ListConstruct %int16, %seq_len, %int64 : (!torch.int, !torch.int, !torch.int) -\u003e !torch.list\u003cint\u003e\n %q \u003d torch.aten.view %query, %q_shape : !torch.vtensor\u003c[1,16,?,64],f32\u003e, !torch.list\u003cint\u003e -\u003e !torch.vtensor\u003c[16,?,64],f32\u003e\n torch.bind_symbolic_shape %q, [%s], affine_map\u003c()[s0] -\u003e (16, s0, 64)\u003e : !torch.vtensor\u003c[16,?,64],f32\u003e\n\n %k_shape \u003d torch.prim.ListConstruct %int16, %int64, %int256 : (!torch.int, !torch.int, !torch.int) -\u003e !torch.list\u003cint\u003e\n %k \u003d torch.aten.view %key, %k_shape : !torch.vtensor\u003c[1,16,64,256],f32\u003e, !torch.list\u003cint\u003e -\u003e !torch.vtensor\u003c[16,64,256],f32\u003e\n %scores_3d \u003d torch.aten.bmm %q, %k : !torch.vtensor\u003c[16,?,64],f32\u003e, !torch.vtensor\u003c[16,64,256],f32\u003e -\u003e !torch.vtensor\u003c[16,?,256],f32\u003e\n torch.bind_symbolic_shape %scores_3d, [%s], affine_map\u003c()[s0] -\u003e (16, s0, 256)\u003e : !torch.vtensor\u003c[16,?,256],f32\u003e\n\n %scores_shape \u003d torch.prim.ListConstruct %int1, %int16, %seq_len, %int256 : (!torch.int, !torch.int, !torch.int, !torch.int) -\u003e !torch.list\u003cint\u003e\n %scores \u003d torch.aten.view %scores_3d, %scores_shape : !torch.vtensor\u003c[16,?,256],f32\u003e, !torch.list\u003cint\u003e -\u003e !torch.vtensor\u003c[1,16,?,256],f32\u003e\n torch.bind_symbolic_shape %scores, [%s], affine_map\u003c()[s0] -\u003e (1, 16, s0, 256)\u003e : !torch.vtensor\u003c[1,16,?,256],f32\u003e\n\n %result \u003d torch.aten.add.Tensor %scores, %mask_bias, %int1 : !torch.vtensor\u003c[1,16,?,256],f32\u003e, !torch.vtensor\u003c[?,256],f32\u003e, !torch.int -\u003e !torch.vtensor\u003c[1,16,?,256],f32\u003e\n torch.bind_symbolic_shape %result, [%s], affine_map\u003c()[s0] -\u003e (1, 16, s0, 256)\u003e : !torch.vtensor\u003c[1,16,?,256],f32\u003e\n return %result : !torch.vtensor\u003c[1,16,?,256],f32\u003e\n }\n}\n\n```\n\u003c/details\u003e\n\nCompile command:\n```\niree-compile \\\n mask_slice_qk_repro.mlir \\\n -o mask_slice_qk_repro.vmfb \\\n --iree-input-type\u003dauto \\\n --iree-hal-target-device\u003dlocal \\\n --iree-opt-data-tiling\u003dtrue \\\n --iree-llvmcpu-enable-ukernels\u003dall \\\n --iree-hal-local-target-device-backends\u003dllvm-cpu \\\n --iree-hal-local-host-device-backends\u003dllvm-cpu \\\n --iree-llvmcpu-target-cpu-features\u003dhost \n```\n\nAssisted by Codex 5.5\n\n---------\n\nSigned-off-by: Juan Ignacio Pisula \u003cpisula@roofline.ai\u003e" }, { "commit": "be57650d3723e4b8b44a341bd007fcb02062dd5b", "tree": "2c20874109b74792eb3d5c618c48aa79d71c4ac3", "parents": [ "6ec0a37c41c0dec313b5f69df6238370e07e303a" ], "author": { "name": "Benoit Jacob", "email": "jacob.benoit.1@gmail.com", "time": "Wed Jul 01 10:36:30 2026 -0400" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Jul 01 16:36:30 2026 +0200" }, "message": "[Codegen][CPU] Drop the ACC stride from the inner_tiled ukernel ABI. (#24652)\n\nNew bottom of the LLVMCPU C-ukernel stack.\n\nThe ACC stride threaded to the C ukernels is always a compile-time\nconstant\nequal to one intrinsic\u0027s ACC fragment size (the data-tiled ACC tile is\ncontiguous), so it folds to a constant after inlining and carries no\ninformation the intrinsic-specific ukernel doesn\u0027t already encode. This\ndrops\nit:\n\n- `IREECPUAttrs.cpp`: remove `getAccInnermostCrossIntrinsicDim`; build\nthe\n`ukernel.generic` with `num_strided_outer_dims\u003d0`, so all shaped\noperands\n (LHS, RHS, ACC) lower to `(base, offset)` only.\n- Both seed ukernel `.c` signatures lose the `acc_stride` parameter.\n\nThis addresses review feedback on the now-merged #24569 / #24571 (why\npass a\nper-operand `strided_dims` array, and why pass an ACC stride that\u0027s\nstatically\nknown). It makes the three operands uniform and removes the\n`getAccInnermostCrossIntrinsicDim` swizzle machinery.\n\nVerified: the lowered `llvm.call` to the ukernel now has no stride\nargument,\nand the ukernel lit tests (`lower_inner_tiled_to_bitcode_ukernel*`,\n`e2e_inner_tiled_pipeline`, `select_ukernel`) pass.\n\nProgress towards https://github.com/iree-org/iree/issues/24574.\n\nSigned-off-by: Benoit Jacob \u003cjacob.benoit.1@gmail.com\u003e" }, { "commit": "6ec0a37c41c0dec313b5f69df6238370e07e303a", "tree": "4c6d0e4b57fc1bf877d463629122f6ca7b5d8590", "parents": [ "50d0addfb49254e0b7b746959b360c79437281cc" ], "author": { "name": "Artem Gindinson", "email": "gindinson@roofline.ai", "time": "Wed Jul 01 15:32:10 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Jul 01 15:32:10 2026 +0200" }, "message": "[Website] Update copyright year in the global footer (#24657)" }, { "commit": "50d0addfb49254e0b7b746959b360c79437281cc", "tree": "d98b2ce8426330b41fac66b8e42e4aa0be98171a", "parents": [ "1781228b16ee6516eba762398197c62945473435" ], "author": { "name": "Stefan Schuermans", "email": "schuermans@roofline.ai", "time": "Wed Jul 01 13:24:42 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Jul 01 13:24:42 2026 +0200" }, "message": "[Docs][Website] Add instructions of how to integrate newer LLVM (#24631)\n\nSigned-off-by: Stefan Schuermans \u003cschuermans@roofline.ai\u003e" }, { "commit": "1781228b16ee6516eba762398197c62945473435", "tree": "cc2e7bb0ef3eef8d20ecd0c7eefbc6d8dae2412a", "parents": [ "a4d0287253fbe7211f545cda304b487218c2a711" ], "author": { "name": "Christopher McGirr", "email": "mcgirr@roofline.ai", "time": "Wed Jul 01 13:22:53 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Jul 01 13:22:53 2026 +0200" }, "message": "[Codegen][DispatchCreation] Separate dispatch for iree_linalg_ext.scan producers (#24651)\n\nThis fix is necessitated by lack of fusion support for LinalgExt Scan -\nsince the default LLVMCPU tiling does not respect the fusability of\nproducer ops, nor the limit for stack-bound allocations, we force this\nnon-fusable \"cumulative reduction\"-style operation to be dispatched\nseparately from non-trivial linalg operations.\n\n---------\n\nCo-authored-by: Artem Gindinson \u003cgindinson@roofline.ai\u003e" }, { "commit": "a4d0287253fbe7211f545cda304b487218c2a711", "tree": "ed15bd28cc2de4925e76a46dd3e72d6fb7c0bd1f", "parents": [ "540008c4aa3f6a2c6e55a054a33f24bd85144d97" ], "author": { "name": "WMC", "email": "tnwilly@gmail.com", "time": "Tue Jun 30 19:35:33 2026 +0800" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jun 30 13:35:33 2026 +0200" }, "message": "[CUDA][LLVMGPU] Fix sm_120 WGP params and add BF16 mma.sync coverage (#24648)\n\n## Description\n\nFixes a correctness issue in `getSM120WgpDetails()` carried over from\nthe Ampere placeholder, consolidates BF16 test coverage into existing\narchitecture-scoped files, and extends sm_120 tests with a\nmixed-precision case.\n\n- **BF16 mma.sync fix**: `NV_MMA_SYNC_F32_16x8x16_BF16` was missing from\nsm_120\u0027s `mmaOps` despite being supported from Ampere onwards. sm_121\nalready advertises this intrinsic. Without this fix, bf16 × bf16 → f32\nmatmuls silently fall back to SIMT tiling on sm_120.\n\n- **Test consolidation**: Per the reviewer\u0027s suggestion, tests no longer\nhave their own per-architecture files. Instead they are folded into the\nexisting architecture-scoped test files.\n\n## Testcases\n\n1. config_tile_and_fuse_sm80.mlir / config_tile_and_fuse_sm120.mlir:\neach gets a new BF16 section verifying that bf16 × bf16 → f32 selects\n`NV_MMA_SYNC_F32_16x8x16_BF16` at the config stage.\n\n1. config_tile_and_fuse_sm120.mlir: adds a mixed-precision f32 × bf16 →\nf32 case to verify the SIMT fallback path when no MMA intrinsic matches\nthe operand types.\n\n1. pipeline_tile_and_fuse_mma_sync.mlir: adds a shared BF16 pipeline\nlowering section that covers both sm_80 and sm_120, verifying\n`nvgpu.mma.sync` is generated with the correct shape.\n\n1. target_device_features.mlir: expands the SM120 metadata check to a\nfull wgp attribute check (mma list, workgroup sizes, memory limits),\nmatching the granularity of the existing SM89 check.\n\n1. bf16_mma_sm80.mlir: deleted — coverage moved into the files above.\n\n---------\n\nSigned-off-by: weimin023 \u003ctnwilly@gmail.com\u003e" }, { "commit": "540008c4aa3f6a2c6e55a054a33f24bd85144d97", "tree": "04d901586f52d7a333dcabdd706cad1c2e2edde2", "parents": [ "42f300cbf843982f52e3ee73d35c5d17f4a84d71" ], "author": { "name": "Alex Vasile", "email": "48962821+Alex-Vasile@users.noreply.github.com", "time": "Mon Jun 29 09:01:46 2026 -0400" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jun 29 15:01:46 2026 +0200" }, "message": "[Metal] Fix indirect dispatch offset for sub-allocated parameter buffers (#24644)\n\niree_hal_metal_command_buffer_prepare_dispatch resolved the\nindirect-dispatch workgroup-count buffer offset as just\nconfig.workgroup_count_ref.offset, dropping\niree_hal_buffer_byte_offset(buffer) -- the base offset of the parameter\nbuffer within its backing allocation. This is inconsistent with the\nsibling descriptor path in the same function (which adds byte_offset)\nand with every other backend: Vulkan and amdgpu route all offsets\nthrough a shared resolver that adds byte_offset, and the local HAL\nresolves through iree_hal_buffer_map_range. When the indirect-parameter\nbuffer is a sub-allocation with a non-zero base offset, the dispatch\nread the three workgroup-count uint32s from the wrong address and ran a\nwrong grid.\n\nThe bug was latent because the Metal allocator returns standalone root\nbuffers (byte_offset\u003d\u003d0) and the cross-backend CTS indirect-parameters\ntests allocate the parameter buffer directly at offset 0.\n\nAdd byte_offset so the source offset matches the descriptor path and the\nother backends:\nworkgroups_offset \u003d\niree_hal_buffer_byte_offset(config.workgroup_count_ref.buffer) +\nconfig.workgroup_count_ref.offset;\n\nAdds CTS regression test\nDispatchIndirectParametersTest.SubAllocatedParameterBuffer, which\nreferences the workgroup counts through an iree_hal_buffer_subspan at a\nnon-zero base offset (placing deliberately-wrong counts at offset 0 so a\nbase-offset drop reads a deterministic grid instead of garbage). This is\nthe only test shape that catches the bug, and it exercises it on every\nbackend that supports sub-allocated buffers (Metal, Vulkan, amdgpu).\n\nSigned-off-by: Alex Vasile\n\u003c48962821+Alex-Vasile@users.noreply.github.com\u003e\n\nSigned-off-by: Alex Vasile \u003c48962821+Alex-Vasile@users.noreply.github.com\u003e" }, { "commit": "42f300cbf843982f52e3ee73d35c5d17f4a84d71", "tree": "829c00481d5cd634a409731e1cbe133e628183c4", "parents": [ "fa27b1c0fcc1122ec5a3c11a50c9a85ab264bf8b" ], "author": { "name": "Alex Vasile", "email": "48962821+Alex-Vasile@users.noreply.github.com", "time": "Mon Jun 29 08:56:43 2026 -0400" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jun 29 14:56:43 2026 +0200" }, "message": "[Metal] Fix staging buffer overflow on large update_buffer uploads (#24643)\n\nupdate_buffer payloads were appended into the single device-shared,\nfixed-capacity (default 128 KiB) staging buffer. Its offset only resets\nwhen all command buffers using it are destroyed, so an oversized host\nupload chunked by the generic queue_emulated_update (e.g. a ~1 MiB\nupload split into 64 KiB pieces, all recorded into one command buffer)\nexhausts the region on the third chunk and fails with\nRESOURCE_EXHAUSTED. This also forced bulk updates to compete with\ndispatch argument buffers for the budget the 128 KiB constant was sized\nfor.\n\nKeep the shared staging buffer as an opportunistic fast path for\npayloads that fit, and spill to a dedicated shared-storage MTLBuffer\nwhen one does not fit the remaining capacity. Dedicated buffers are\nretained for the command buffer\u0027s lifetime (released in\ncommand_buffer_reset, which runs only after the GPU completes via the\nsubmission resource set) and used as the blit-copy source. This handles\narbitrary update sizes and counts without touching the driver-generic\nqueue_emulation chunking, matching how Vulkan and CUDA capture update\npayloads per-command rather than in a shared fixed region.\n\nFixes the aligned16_mib sub-case of\nCTS/CommandBufferCopyBufferTest.CopySizeAndAlignmentClasses/metal.\n\nSigned-off-by: Alex Vasile\n\u003c48962821+Alex-Vasile@users.noreply.github.com\u003e\n\nSigned-off-by: Alex Vasile \u003c48962821+Alex-Vasile@users.noreply.github.com\u003e" }, { "commit": "fa27b1c0fcc1122ec5a3c11a50c9a85ab264bf8b", "tree": "70250c6716f1cf9ba2723199f45d8c1cad2d096f", "parents": [ "e43aaf54aa59924a8cab4f92354c65c0fe5df9aa" ], "author": { "name": "Alex Vasile", "email": "48962821+Alex-Vasile@users.noreply.github.com", "time": "Mon Jun 29 08:55:49 2026 -0400" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jun 29 14:55:49 2026 +0200" }, "message": "[Metal] Carry export name separately from MSL entry point for name lookup (#24642)\n\nspirv-cross rewrites SPIR-V entry point names to be legal MSL/C\nidentifiers when serializing Metal executables: \u0027.\u0027 characters (codegen\ndispatch names like _dot_general_matmul_i32.i32.i32_...) become \u0027_\u0027, and\nreserved \u0027__\u0027 prefixes (stream builtins like __builtin_splat_i64) are\ndropped. The MetalSPIRV target stored only the rewritten MSL function\nname in PipelineDef.entry_point, and the runtime loaded pipeline-\u003ename\nfrom that same field -- so hal.executable.lookup.function, which\nreferences the original un-rewritten hal.executable.export symbol name,\ncould never match for any export whose name spirv-cross rewrites. This\nbroke every metal-spirv e2e test using such exports\n(dot/dot_general/convolution matmul kernels and\ncompare/dynamic_slice/gather stream builtins).\n\nAdd a dedicated always-present name field to PipelineDef carrying the\ncanonical hal.executable.export symbol name (populated from\nexportOp.getName() in the compiler), appended at the end of the table\nfor backward-compatible vtable layout. The runtime now sources\npipeline-\u003ename (used by lookup_function_by_name) from this field,\nkeeping entry_point as the MTLFunction name for -[MTLLibrary\nnewFunctionWithName:]. The loader falls back to entry_point when name is\nabsent for compatibility.\n\nVerified: dot_general (8/8), compare (15/15), and the full Metal CTS\nsuite\n(command_buffer_tests/queue_tests/dispatch_tests/queue_dispatch_tests,\n4/4) pass. Signed-off-by: Alex Vasile\n\u003c48962821+Alex-Vasile@users.noreply.github.com\u003e\n\nSigned-off-by: Alex Vasile \u003c48962821+Alex-Vasile@users.noreply.github.com\u003e" }, { "commit": "e43aaf54aa59924a8cab4f92354c65c0fe5df9aa", "tree": "cbe83c8bd0975b9d9938ec76661d0a05f2dc8568", "parents": [ "51bd22fe7d6e3cf72692d367b84d7c3b4eb8f35b" ], "author": { "name": "Alex Vasile", "email": "48962821+Alex-Vasile@users.noreply.github.com", "time": "Mon Jun 29 06:04:02 2026 -0400" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jun 29 12:04:02 2026 +0200" }, "message": "[Metal] Fix indirect dispatch retaining stack garbage as a resource (#24641)\n\niree_hal_metal_command_buffer_prepare_dispatch built a resources[2]\narray for direct/indirect dispatch but passed \u0026executable (the address\nof the parameter) to iree_hal_resource_set_insert instead of the\nresources array. For indirect dispatch (resource_count\u003d\u003d2) this read the\nstack word adjacent to the parameter and retained it as a resource,\ncorrupting the resource set and crashing on command-buffer teardown\n(release dereferenced a NULL vtable).\n\nPass resources so both the executable and the indirect workgroup-count\nbuffer are retained correctly. Fixes the DispatchIndirectParameters and\nQueueDispatchIndirectParameters CTS segfaults (ctest #1307, #1309).\n\nSigned-off-by: Alex Vasile\n\u003c48962821+Alex-Vasile@users.noreply.github.com\u003e\n\nSigned-off-by: Alex Vasile \u003c48962821+Alex-Vasile@users.noreply.github.com\u003e" }, { "commit": "51bd22fe7d6e3cf72692d367b84d7c3b4eb8f35b", "tree": "3ba41a8b34ca76dda2a4d3d9ff4874e3345a7d31", "parents": [ "954f90d2f53b22ff8b347ae215d58b6cb1ca1cb3" ], "author": { "name": "Alex Vasile", "email": "48962821+Alex-Vasile@users.noreply.github.com", "time": "Mon Jun 29 06:00:22 2026 -0400" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jun 29 12:00:22 2026 +0200" }, "message": "[Metal] Fix copy_buffer_1byte dispatch grid (#24640)\n\ncopy_buffer_1byte silently dropped the trailing ~3/4 of every copy that\nfell back to the compute-kernel path. The kernel copies one byte per\nthread, but its dispatch grid was sized as ceil(length / (workgroup_size\n* 4)) -- a quarter of the required ceil(length / workgroup_size)\nworkgroups -- so only the first min(ceil(length/128)*32, length) bytes\nwere written and the tail was left untouched. The bounds guard `if (id\n\u003e\u003d spec.length) return` prevents over-run but cannot launch the missing\nthreads.\n\nOn macOS the compute path is taken whenever the source offset, target\noffset, or length is not a multiple of 4 (the Metal blit fast-path\nrequires all three 4-byte aligned). It is also the path behind the\nstaging-\u003edevice upload\n(iree_hal_metal_command_buffer_prepare_update_buffer), so non-4-aligned\nsource uploads were truncated too -- a device copy then read a zeroed\nsource tail.\n\nThe *4 multiplier is correct for the fill kernels (fill_buffer_16byte /\nfill_buffer_4byte / fill_buffer_1byte process 16/4/4 bytes per thread\nrespectively), which is where it was copied from; copy_buffer_1byte is a\nflat 1-byte-per-thread loop with no such expansion.\n\nFix (dispatch only -- the copy_buffer_1byte.metal kernel is unchanged):\nsize the grid as ceil(length / workgroup_size) so the launched thread\ncount (ceil(length/32) * 32) covers every byte. The existing `if (id \u003e\u003d\nspec.length) return` guard masks the surplus threads in the final\nworkgroup.\n\nVerified:\nCTS/CommandBufferCopyBufferTest.CopySizeAndAlignmentClasses/metal now\npasses all alignment/size sub-cases that previously truncated\n(offset/length not a multiple of 4; lengths 31/32/33/.../65536 across\nall alignment classes). The aligned16_mib sub-case still fails,\nindependently, from a staging-buffer capacity issue (128 KiB staging\nbuffer vs. a 1 MiB single-command-buffer upload), not from this dispatch\nsizing. Signed-off-by: Alex Vasile\n\u003c48962821+Alex-Vasile@users.noreply.github.com\u003e\n\nSigned-off-by: Alex Vasile \u003c48962821+Alex-Vasile@users.noreply.github.com\u003e" }, { "commit": "954f90d2f53b22ff8b347ae215d58b6cb1ca1cb3", "tree": "10419b00ad1193ee823a131e57e8c8916fefb114", "parents": [ "fbf06b1c5baf527c58fe360aa4e573e58abd6238" ], "author": { "name": "Alex Vasile", "email": "48962821+Alex-Vasile@users.noreply.github.com", "time": "Mon Jun 29 05:45:55 2026 -0400" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jun 29 11:45:55 2026 +0200" }, "message": "[Metal] Fix fill_buffer_1byte edge handling for unaligned offsets (#24639)\n\nfill_buffer_1byte silently corrupted data for any buffer_offset % 4 in\n{1, 3}, and corrupted neighboring bytes for fills contained within a\nsingle 4-byte word. Two independent defects, both in the edge handling:\n\n1. left_mask selected the wrong byte positions. It was computed as ~((1\n\u003c\u003c (8 * (4 - left_byte_count))) - 1), selecting byte positions [4-k, 4)\nof the left word. But the left edge must overwrite the high (4-k) bytes,\ni.e. positions [k, 4), so the mask must be ~((1 \u003c\u003c (8 * k)) - 1). The\nstray \"4 -\" is the asymmetry with the correct right_mask (which uses\nright_byte_count directly). For k in {1, 3} the wrong mask is a\nsymmetric 2-byte misplacement (|4-2k| \u003d\u003d 2):\n- offset % 4 \u003d\u003d 1: under-fill -- the leading 2 in-region bytes are left\nstale.\n- offset % 4 \u003d\u003d 3: underrun -- the 2 bytes immediately preceding the\nregion are clobbered.\n\n2. When the entire fill range fits within one 32-bit word, the left and\nright read-modify-write blocks both attacked that same word with masks\nassuming a complete edge, writing pattern bytes outside [offset, offset\n+ length). Reachable via short 1/2-byte-pattern fills (duplicated to 4\nbytes on the host) whose length lands within one word.\n\nBeyond the k \u003d\u003d 0 case (handled by fill_buffer_4byte), the kernel was\ncorrect only for offset % 4 \u003d\u003d 2 with length \u003e\u003d 2.\n\nFix (kernel-only):\n\n- Correct left_mask: use left_byte_count instead of (4 -\nleft_byte_count).\n- Add a single-word guard: when left_start \u003d\u003d right_start, perform one\nread-modify-write over bytes [left_byte_count, right_byte_count) using\nmask \u003d left_mask \u0026 right_mask; otherwise keep the existing separate\nleft/right blocks. This also makes length \u003d\u003d 0 a safe no-op via mask\ncollapse, where the original corrupted up to 4 neighbor bytes.\n\nNo host-side change: the middle word range [middle_start, right_start)\nand thus the thread-count requirement are unchanged, and the existing\ndispatch sizing in builtin_executables.m already over-dispatches safely.\n\nVerified:\nCTS/CommandBufferFillBufferTest.FillSizeAlignmentAndPatternClasses/metal\nand CTS/QueueTransferTest.FillSizeAlignmentAndPatternClasses/metal now\npass (previously failed with a 2-byte under-fill at offset%4\u003d\u003d1 and a\n2-byte underrun at offset%4\u003d\u003d3); all *Fill* cases pass (22/22 in\ncommand_buffer_tests, 8/8 in queue_tests).\n\nSigned-off-by: Alex Vasile \u003c48962821+Alex-Vasile@users.noreply.github.com\u003e" }, { "commit": "fbf06b1c5baf527c58fe360aa4e573e58abd6238", "tree": "529d0a05ff0afeed4a7e7f6023b4e57d7f20cd4e", "parents": [ "8643a6f574c59ca96e159f8ee60264d8bba31007" ], "author": { "name": "Umer Ahmad Khan", "email": "149548566+UmerAhmad211@users.noreply.github.com", "time": "Mon Jun 29 13:49:53 2026 +0500" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jun 29 08:49:53 2026 +0000" }, "message": "[Samples] Fix error by replace arrange with arange (#24647)\n\nFixes #24646 by replacing instances of ```arrange``` with ```arange```\nin the file.\n\n---------\n\nSigned-off-by: UmerAhmad211 \u003cumerahmed824@gmail.com\u003e" }, { "commit": "8643a6f574c59ca96e159f8ee60264d8bba31007", "tree": "dfa9e746470a7fdd3bf79fa6f4272299c6452bc9", "parents": [ "6e7be0d3e6bd6b472cc8106c9b5893ac36b70b90" ], "author": { "name": "Corentin Kerisit", "email": "corentin.kerisit@gmail.com", "time": "Mon Jun 29 09:10:40 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jun 29 09:10:40 2026 +0200" }, "message": "[Runtime] Include base API header from futex.h (#24630)\n\n`futex.h` uses base API types and macros provided through\n`iree/base/api.h`, including status, attributes, config, and time\ndefinitions.\n\nThis includes the public base API umbrella instead of including those\nbase headers directly. `target_platform.h` remains explicit because\n`futex.h` directly depends on platform detection macros.\n\nThis makes bazel layering check fail, hence the fix.\n\nSigned-off-by: Corentin Kerisit \u003ccorentin.kerisit@gmail.com\u003e" }, { "commit": "6e7be0d3e6bd6b472cc8106c9b5893ac36b70b90", "tree": "4bcccd292b452b3dc6532cbe1af176070e810243", "parents": [ "fca4d82e26db4106740e20b08fef2e58eb9fbf6a" ], "author": { "name": "maxbartel", "email": "bartel@roofline.ai", "time": "Mon Jun 29 07:58:47 2026 +0100" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jun 29 08:58:47 2026 +0200" }, "message": "[CI] Remove mi355 job after the runner was removed (#24632)\n\nThe runner got moved to a different project. This removes the job to not\nrun into timeouts on main all the time." }, { "commit": "fca4d82e26db4106740e20b08fef2e58eb9fbf6a", "tree": "ebdd90e221f3c4ce871eb5a04b3fc6a57e973101", "parents": [ "7bbe56d4fe1d852a4e01483bb0e42ed1984ae4a8" ], "author": { "name": "Ege Beysel", "email": "beysel@roofline.ai", "time": "Thu Jun 25 15:07:12 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Jun 25 15:07:12 2026 +0200" }, "message": "Integrate LLVM to llvm/llvm-project@22da7f929139 (#24629)\n\nClean integrate, no carry-over revert.\n\nBump to\n[llvm/llvm-project@22da7f929139](https://github.com/llvm/llvm-project/commit/22da7f929139).\n\nSigned-off-by: Ege Beysel \u003cbeyselege@gmail.com\u003e" }, { "commit": "7bbe56d4fe1d852a4e01483bb0e42ed1984ae4a8", "tree": "8eb7def1d0fed141ebe474b8102ff83837ee3417", "parents": [ "a33726400ea0505c5f189abcad37416af5ac2ca1" ], "author": { "name": "Michael Interlandi", "email": "43190101+Minterl@users.noreply.github.com", "time": "Thu Jun 25 05:57:56 2026 -0400" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Jun 25 11:57:56 2026 +0200" }, "message": "[Docs] Add notice about pthread sync fallbacks (#24618)\n\nThe generic platform with IREE_ENABLE_THREADING OFF requires pthread\ntypes/functions:\n\n `pthread_once_t` / `pthread_once`\n `pthread_mutex_t` / `pthread_mutex_*`\n `pthread_cond_t` / `pthread_cond_*`\n\nAdded a notice in the bare metal runtime documentation about the\ndependency.\n\nrelates to #24604\n\n---------\n\nSigned-off-by: Mike Interlandi \u003c43190101+Minterl@users.noreply.github.com\u003e\nCo-authored-by: Tobias Fuchs \u003c9053039+devtbi@users.noreply.github.com\u003e" }, { "commit": "a33726400ea0505c5f189abcad37416af5ac2ca1", "tree": "e063f2503e22ed240d7e76562f8ddfd7adb266c8", "parents": [ "6b78497e50092a09c97c3af683bed0c41fba5293" ], "author": { "name": "Alex", "email": "hanweng9@gmail.com", "time": "Wed Jun 24 10:58:28 2026 -0400" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Jun 24 14:58:28 2026 +0000" }, "message": "[GlobalOpt] Fix crash in RaiseSpecialOps on buffer-semantics named ops (#24626)\n\n## Problem\n\nPassing a `linalg.matmul` (or any named contraction/convolution op) with\n**memref / buffer operands** to `iree-compile` crashes with a hard\nassert instead of a clean diagnostic:\n\n```\nAssertion failed: (index \u003c size() \u0026\u0026 \"invalid index into type range\"),\nfunction operator[], file TypeRange.h, line 156.\n...\nNamedImplicitCastOpConversion\u003clinalg::ContractionOpInterface\u003e::matchAndRewrite(...)\n```\n\n`NamedImplicitCastOpConversion::matchAndRewrite` in\n`GlobalOptimization/RaiseSpecialOps.cpp` reasons about the op\u0027s results\n(`getResultTypes()[0]`) and rewrites its body region, both of which\nassume tensor semantics. A buffer-semantics linalg op writes to an\noutput buffer and has **zero results**, so `getResultTypes()[0]` indexes\nan empty `TypeRange` and aborts.\n\n## Fix\n\nBail out via `hasPureTensorSemantics()` before touching results,\nmatching the guards already used elsewhere in this file (e.g. lines 48,\n231). The op is left untouched and compilation proceeds normally.\n\n## Verification (local, llvm-cpu)\n\nA/B on identical current `main` sources, exact reproducer from the\nissue:\n\n| Build | `iree-compile ... memref matmul` |\n|---|---|\n| unfixed (`main`) | exit **134**, assert in\n`NamedImplicitCastOpConversion` |\n| fixed (this PR) | exit **0**, compiles cleanly to a valid `.vmfb` |\n\n- Added lit test `@matmul_memref_no_crash` in `raise_special_ops.mlir`.\n- Full `raise_special_ops.mlir` lit suite passes.\n\nFixes #24624\n\nSigned-off-by: Alex-Wengg \u003chanweng9@gmail.com\u003e" }, { "commit": "6b78497e50092a09c97c3af683bed0c41fba5293", "tree": "7265a23fcf2e13e59c078f00cdbd5d32936f6597", "parents": [ "64b263ba6bcf0cf7846e6d6ff51a7b5060207503" ], "author": { "name": "Benoit Jacob", "email": "jacob.benoit.1@gmail.com", "time": "Wed Jun 24 09:31:11 2026 -0400" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Jun 24 09:31:11 2026 -0400" }, "message": "[Codegen][CPU] End-to-end-through-codegen lit test for ukernel framework. (#24571)\n\nCloses the loop on the new C-bitcode ukernel framework with an\n`iree-opt` lit test that drives the full LLVMCPU codegen pipeline on an\n`inner_tiled` rooted dispatch wrapped in the standard\n`hal.executable.variant` + binding-subspan structure, and asserts the\nwhole chain end-to-end:\n\n- Bitcode reaches the dispatch\u0027s `hal.executable.variant` as a\nfirst-class `objects(...)` attribute (the long-lived home).\n- `llvm.func @iree_uk_mma_…` is declared with `hal.import.bitcode \u003d\ntrue`, the flag that tells `RewriteExternCallOpToDynamicImportCallOp` to\nskip the runtime-import-table indirection.\n- A direct `llvm.call @iree_uk_mma_…` replaces the original\n`inner_tiled` — no `__import_ordinal_iree_uk_mma_…` (which would mean we\naccidentally re-used the legacy runtime-resolved path), no leftover\n`inner_tiled`, no leftover `ukernel.generic`.\n\nTo make that chain work, two pieces had to land alongside the test:\n\n* `UKernelProviderAttr::createAndReplaceWithUkernelOp` now actually\nbuilds the `UKernelGenericOp` (returning `success`, not `nullopt`),\nsetting `fn_def_attrs \u003d {hal.import.bitcode \u003d true}` on it. That flag\npropagates onto the `func.func` declaration that\n`LowerUKernelOpsToCalls` synthesizes, and through it onto the\n`llvm.func` that `ConvertToLLVM` produces. Without this, the\n\"self-contained bitcode\" property of the new framework would not hold —\nevery external call would be routed through the runtime import table\njust like the legacy mmt4d ukernels.\n\n* Bitcode lookup-and-attach is factored into a public helper\n`IREE::CPU::attachUKernelBitcodeOnOp`, called both from\n`LLVMCPUSelectUKernels` (at kernel-config time, mirroring GPU\u0027s\n`ensureUKernelBitcodeAndFinalizeConfig`) and from the provider itself\n(as a backstop for the BYO / hand-written-IR paths). It attaches the\nbitcode both as a `hal.executable.objects` discardable attribute on the\nop (the GPU-aligned shape) *and* directly on the enclosing\n`hal.executable.variant`\u0027s `objects` operand attribute (the durable\nhome, sidestepping passes that strip discardable attrs through\n`ConvertToLLVM`).\n\nProgress towards https://github.com/iree-org/iree/issues/24574.\n\nSigned-off-by: Benoit Jacob \u003cjacob.benoit.1@gmail.com\u003e\nCo-authored-by: Claude Opus 4.7 \u003cnoreply@anthropic.com\u003e" }, { "commit": "64b263ba6bcf0cf7846e6d6ff51a7b5060207503", "tree": "9b925e73f23c55ec382f578effc2a4c3074ade62", "parents": [ "a45adeaa6115e446c898e6eb21fb6edc0e65ddc4" ], "author": { "name": "Lekkala_Sravya-mcw", "email": "lekkala.sravya@multicorewareinc.com", "time": "Wed Jun 24 17:26:06 2026 +0530" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Jun 24 13:56:06 2026 +0200" }, "message": "[Flow] Fold static flow.tensor.empty shapes into dims (#24622)\n\nThis PR Adds a canonicalization pattern for `flow.tensor.empty` that\nfolds constant dynamic dimension operands into the static result shape.\n\n**Example :**\n\n%0 \u003d flow.tensor.empty : tensor\u003c?x4xf32\u003e{%c8}\n\n**canonicalizes to:**\n\n%0 \u003d flow.tensor.empty : tensor\u003c8x4xf32\u003e\n%cast \u003d tensor.cast %0 : tensor\u003c8x4xf32\u003e to tensor\u003c?x4xf32\u003e\n\nThe cast preserves the original result type for existing users while\nallowing downstream canonicalization to use the refined static shape.\n\n---------\n\nSigned-off-by: LekkalaSravya3 \u003clekkala.sravya@multicorewareinc.com\u003e" }, { "commit": "a45adeaa6115e446c898e6eb21fb6edc0e65ddc4", "tree": "d758ea5d64f0c889151186566c17cc27278928c5", "parents": [ "04599de77c74088726c8b9d8538ba19c0e235bb8" ], "author": { "name": "Ege Beysel", "email": "beysel@roofline.ai", "time": "Tue Jun 23 16:52:26 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jun 23 16:52:26 2026 +0200" }, "message": "Integrate LLVM to llvm/llvm-project@9550cd76cade (#24623)\n\nClean integrate, no reverts carried over.\n\nSigned-off-by: Ege Beysel \u003cbeyselege@gmail.com\u003e" }, { "commit": "04599de77c74088726c8b9d8538ba19c0e235bb8", "tree": "994a4c93209c7c0068f9f61cf1ced6c468ef217b", "parents": [ "ac077d8815292c93149ac387a33ca4a844d3641e" ], "author": { "name": "Christopher McGirr", "email": "mcgirr@roofline.ai", "time": "Tue Jun 23 09:04:07 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jun 23 09:04:07 2026 +0200" }, "message": "[Codegen][GPU] Add TargetDetails for Nvidia Ada Arch (#24616)\n\nAda architecture seems to be slightly different to the previous\ngeneration. With a different number of streaming multiprocessors. This\nPR adds support for RTX 4000s series GPUs." }, { "commit": "ac077d8815292c93149ac387a33ca4a844d3641e", "tree": "156cb3fce8a7455c66b07c377fe10e28020fc363", "parents": [ "6971dfb7570b203ef0bd6544f78b06f4ec7629e7" ], "author": { "name": "Alex", "email": "hanweng9@gmail.com", "time": "Mon Jun 22 16:17:50 2026 -0400" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jun 22 22:17:50 2026 +0200" }, "message": "[NFC] Remove the llvm-external-projects/iree-dialects directory (#24466) (#24612)\n\n## Overview\n\nRemoves the `llvm-external-projects/iree-dialects` directory now that\nnothing in the compiler or runtime depends on it.\n\nThis is the final step of #24466. The production dependencies were\nretired in #24543 and predecessors:\n- the softmax matcher was reimplemented natively in\n`GlobalOptimization/RaiseSpecialOps`,\n- `ErrorCheckingTrackingListener` was moved into `Codegen/Common/`,\n- `DropSchedulePass` was moved into `Codegen/Common/`,\n- the callback-matcher transform ops\n(`transform.iree.register_match_callbacks` / `match_callback` /\n`take_first` / `emit_remark`) and their tests were dropped.\n\n## Changes\n\n- Delete `llvm-external-projects/iree-dialects/`.\n- Drop the `iree_llvm_add_external_project(mlir-iree-dialects ...)` call\nfrom the top-level `CMakeLists.txt`.\n- Remove the dead iree-dialects target conversion from `bazel_to_cmake`.\n- Drop the `IREEDialects*` Python sources + include path from\n`compiler/bindings/python/CMakeLists.txt`, the `_ireeDialects`\n`CMakeExtension` from `compiler/setup.py`, and the `iree_dialects.rst`\nAPI doc.\n- Remove the `iree-dialects-doc` build step from the website doc\ngenerator.\n- Remove the \"Test iree-dialects\" CI steps and the `check-iree-dialects`\ntargets from the ASan/UBSan scripts (and the now-unused\n`test_iree_dialects.sh`).\n\n## Testing\n\n- **Local (Windows + MSVC, Ninja, Release):** CMake configure is clean\nafter the external-project removal only `stablehlo` remains as an\nexternal LLVM project and a full-tree grep finds zero dangling\nreferences. The full `iree-opt` target builds, links, and runs\n(`iree-opt --version` → LLVM 23.0.0git).\n\n---------\n\nSigned-off-by: Alex-Wengg \u003chanweng9@gmail.com\u003e" }, { "commit": "6971dfb7570b203ef0bd6544f78b06f4ec7629e7", "tree": "cea20b7587bd52ba6d8da2599a348ad796a73ae7", "parents": [ "4576683cfe93ff25ea7cdec6c3daefc3ad7825bf" ], "author": { "name": "Christopher McGirr", "email": "mcgirr@roofline.ai", "time": "Mon Jun 22 11:17:01 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jun 22 11:17:01 2026 +0200" }, "message": "[Codegen][GlobalOpt] Detach non-splat constant inits (#24605)\n\nA constant used directly as the `outs` (init/destination) of a\n`linalg.matmul` or convolution e.g. a fully-connected/conv bias imported\nfrom TFLite via TOSA survives into dispatch formation. It is then cloned\ninto the workgroup on the written (output) side and bufferizes as a\nread-only global, which fails workgroup-distribution verification with\nthe following error:\n\n```\n\u0027linalg.generic\u0027 op write affecting operations on global resources are restricted to workgroup distributed contexts\n\u0027func.func\u0027 op failed on workgroup distribution verification\n```\n\nThis kind of IR was seen in TFLite -\u003e TOSA conversion flows and and the\nIR below is an example of that:\n\n```mlir\nutil.func public @main(%a: tensor\u003c1x1xf32\u003e, %w: tensor\u003c1x9xf32\u003e) -\u003e tensor\u003c1x9xf32\u003e {\n %bias \u003d arith.constant dense\u003c[[1.0, 1.0, 2.0, 2.0, 3.0, 3.0, 4.0, 4.0, 5.0]]\u003e : tensor\u003c1x9xf32\u003e\n %0 \u003d linalg.matmul ins(%a, %w : tensor\u003c1x1xf32\u003e, tensor\u003c1x9xf32\u003e)\n outs(%bias : tensor\u003c1x9xf32\u003e) -\u003e tensor\u003c1x9xf32\u003e\n util.return %0 : tensor\u003c1x9xf32\u003e\n}\n```\n\nThe chosen solution is to use is the `DetachElementwiseFromNamedOps`\npattern which exists to keep non-writable inits out of dispatches. It\nonly covers two of our three relevant cases. The pass will\n1. Take a non-const init and detach it into a zero-fill plus a trailing\nadd\n2. Take a splat constant init and convert it to a fill.\n\nOur use-case of a non-splat constant init would not be handled. Here we\nextend the elementwise detach pattern so a non-splat constant init is\ndetached the same way a computed init is. A fresh zero-fill is created\nand the constant is added back as a read-only input. This form of IR can\nbe then handled by codegen.\n\nAfter the fix the reproducer compiles and the bias survives read-only:\n\n```\n%bias \u003d arith.constant ... : tensor\u003c1x9xf32\u003e\n%z \u003d linalg.fill ins(%c0 : f32) outs(%empty : tensor\u003c1x9xf32\u003e) -\u003e tensor\u003c1x9xf32\u003e\n%mm \u003d linalg.matmul ins(%a, %w) outs(%z) -\u003e tensor\u003c1x9xf32\u003e\n%0 \u003d linalg.generic ins(%mm, %bias) outs(%z) { ... } // %mm + %bias\n```\n\n---\n\n_Code Examples and Tests Assisted-by Claude_" }, { "commit": "4576683cfe93ff25ea7cdec6c3daefc3ad7825bf", "tree": "296d7ceae7ac8113b574c84cd45e147bcbf0a33b", "parents": [ "59f952c5a83777e78f251e238338d7345a1bfb36" ], "author": { "name": "Artem Gindinson", "email": "gindinson@roofline.ai", "time": "Fri Jun 19 16:11:18 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Jun 19 16:11:18 2026 +0200" }, "message": "[Docs] Remove outdated mlir-iree-dialects path when publishing website (#24611)\n\nRemove copying of an outdated external dialects path.\n\nFollows up on b832562e371b4562d7d2ac9ca283f777ab4b4dfe.\n\nSigned-off-by: Artem Gindinson \u003cgindinson@roofline.ai\u003e" }, { "commit": "59f952c5a83777e78f251e238338d7345a1bfb36", "tree": "5f37f75c087bbc67ae5be7e5ba4a0b6a63bb5919", "parents": [ "b832562e371b4562d7d2ac9ca283f777ab4b4dfe" ], "author": { "name": "Stefan Schuermans", "email": "schuermans@roofline.ai", "time": "Fri Jun 19 13:15:24 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Jun 19 13:15:24 2026 +0200" }, "message": "Integrate LLVM to llvm/llvm-project@1e0899794dd4 (#24610)\n\nAdapted a LLVMCPU and a LLVMGPU codegen test to not expect the\npreviously incorrectly emitted \"nuw\" flag.\nThis has been fixed in LLVM in this commit:\n[mlir][MemRefToLLVM] fix incorrect nuw on GEP/mul when lowering\nmemref.load/store with negative strides (#204309)\n \nFinding the commit that caused the change and understanding the effect\nhas been assisted by Claude Code.\nThe changes to the tests have been manually checked. The strides are\ndynamic, so negative strides are possible and \"nuw\" should not be there.\n\nSigned-off-by: Stefan Schuermans \u003cschuermans@roofline.ai\u003e" }, { "commit": "b832562e371b4562d7d2ac9ca283f777ab4b4dfe", "tree": "0630169bb41739c98d2b1c94893e458c6377f3b2", "parents": [ "963a40467096144f2a9b79712a67f97185a7a2c8" ], "author": { "name": "Alex", "email": "hanweng9@gmail.com", "time": "Fri Jun 19 05:44:55 2026 -0400" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Jun 19 11:44:55 2026 +0200" }, "message": "Move softmax matcher and ErrorCheckingTrackingListener out of iree-dialects (#24466) (#24543)\n\nCloses #24466 (retire the\n`llvm-external-projects/iree-dialects`\ndependency). Relocates the last two pieces of code that still depended\non the NFC directory. Finishing Tasks 1 \u0026 4.\n\n- **[GlobalOpt] Reimplements the softmax matcher within\n`GlobalOptimization/`. Adds `arith.maximumf` support to account for SHLO decompositions.\n- **[Codegen] Move ErrorCheckingTrackingListener** into\n`Codegen/Common/` and de-register `StructuredTransformOpsExtension` from\n`CommonDialectRegistration` and `Interfaces`. Continuation of #24500.\n- Removes llvm-external-projects/iree-dialects as a whole\n\n## Testing\n\nBuilt and lit tested locally on Windows 11 + MSVC 14.44 (VS 2022\nCommunity), Ninja, CMake 3.29, Release with assertions,\n`IREE_TARGET_BACKEND_LLVM_CPU\u003dON`. All changed files compile cleanly.\nThe softmax lit test\n`compiler/src/iree/compiler/GlobalOptimization/test/raise_special_ops.mlir`\npassed. all three variants (`@softmax`, `@softmax_no_rcp`,\n`@softmax_broadcast`) match correctly through the relocated\n`makeSoftmaxMatcher`.\n\n---------\n\nSigned-off-by: Han || Alex \u003c36247722+Alex-Wengg@users.noreply.github.com\u003e\nSigned-off-by: Alex-Wengg \u003chanweng9@gmail.com\u003e" }, { "commit": "963a40467096144f2a9b79712a67f97185a7a2c8", "tree": "4caae6d1979800eb6bc464edda56b6ea9cf04d31", "parents": [ "bbd7080627002b111a76623d49d3ab41c10c410b" ], "author": { "name": "Stefan Schuermans", "email": "schuermans@roofline.ai", "time": "Wed Jun 17 22:48:53 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Jun 17 13:48:53 2026 -0700" }, "message": "Integrate LLVM to llvm/llvm-project@75b7809248cc (#24609)\n\nAdapted region successors\u0027s parent() to constructing from\nop.getOperation() and from isParent() to isOperation() due to LLVM\nupstream change 6e6c296f2014 [mlir] Use explicit op targets for region\nsuccessors (#203552)\n\nAdapting to removal of emitc::ApplyOp, using emitc::AddressOfOp or\nemitc::SubscriptOp + emitc::LoadOp instead ba7be6262c71 [mlir][emitc]\nRemove deprecated apply op (#203712)\n\nThese fixes have been assisted by Claude Code and have been manually\nreviewed.\n\nUpdated torch-mlir submodule as well due to LLVM changes.\n\nSigned-off-by: Stefan Schuermans \u003cschuermans@roofline.ai\u003e" }, { "commit": "bbd7080627002b111a76623d49d3ab41c10c410b", "tree": "31242cba5643080100b606c0cda26478150f804e", "parents": [ "1b1aebbcab41b3022d6af0d635f64fc29bff735e" ], "author": { "name": "Benoit Jacob", "email": "jacob.benoit.1@gmail.com", "time": "Wed Jun 17 10:26:53 2026 -0400" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Jun 17 14:26:53 2026 +0000" }, "message": "[Codegen][CPU] Wire LowerBitcodeUKernels into the Mmt4dTilingExpert pipeline. (#24570)\n\nCompletes the new-style C-ukernel pipeline integration:\n\n* `LLVMCPUTarget.cpp`: install `iree_codegen.ukernel_provider \u003d\n#iree_cpu.ukernel_provider` on every LLVMCPU executable target config\nwhenever `--iree-llvmcpu-enable-llvm-ukernels` is non-empty. This\nmirrors what ROCM does and is what lets the generic\n`LowerBitcodeUKernelsPass` find the CPU provider for the\nbitcode-lookup-and-attach.\n\n* `KernelDispatch.cpp::setRootConfig(InnerTiledOp)`: when\n`selectUKernel` returns a descriptor, set the reduction-dim vector tile\nsize to 0 (untiled) instead of 1 (unrolled). The ukernel\u0027s C function\ntakes the outer K extent as a runtime argument (`k_outer`) and runs the\nK loop itself; pre-unrolling here would both defeat that and bloat the\nIR. Matches the equivalent split in\n`setDataTiledMmaInnerTiledLoweringConfig` on the GPU side.\n\n* `Passes.cpp::addMmt4dTilingExpertPassPipeline`: insert\n`createLowerBitcodeUKernelsPass()` between the parallel-tile and\nreduction-tile passes. A nop when no op carries a `iree_codegen.ukernel`\ndescriptor, so it stays in the default pipeline. The companion\n`LowerUKernelOpsToCalls` already runs after bufferization (in\n`addLowerToLLVMPasses`); together they implement the user\u0027s \"early\n`inner_tiled` -\u003e `ukernel.generic` on tensors; late `ukernel.generic` -\u003e\n`func.call` on memrefs\" split.\n\nLit test (`select_ukernel.mlir`) gains a second RUN line that chains\n`iree-llvmcpu-select-lowering-strategy` with\n`iree-codegen-lower-bitcode-ukernels` and asserts:\n- the `inner_tiled` is rewritten to `iree_codegen.ukernel.generic`\ncarrying the right `iree_uk_mma_x86_avx512bf16_1x16x2_f32_bf16` name;\n- the matching bitcode appears as `hal.executable.objects` (resolved\nfrom the global `EmbeddedDataDirectory` populated at LLVMCPU plugin\ninit);\n- and the original `inner_tiled` is gone, guarding against the rewrite\nsilently no-op\u0027ing on a regression.\n\nAn end-to-end `iree-compile` test would also be desirable, but the\ncurrent pipeline state needs more wiring (workgroup-distribution\nverifier complains about the bufferization-introduced copy ops around\nthe workgroup loop, on both the ukernel and non-ukernel paths) — that\ninvestigation belongs with the follow-up commit that fills in real\nukernel bodies and an actual numerical matmul test.\n\nProgress towards https://github.com/iree-org/iree/issues/24574.\n\nSigned-off-by: Benoit Jacob \u003cjacob.benoit.1@gmail.com\u003e\nCo-authored-by: Claude Opus 4.7 \u003cnoreply@anthropic.com\u003e" }, { "commit": "1b1aebbcab41b3022d6af0d635f64fc29bff735e", "tree": "6cff4431a3aa5145d1b933becb48b5e4b0e87f51", "parents": [ "a67fb36f2bf9e866b10ab4503c0139e1cffec393" ], "author": { "name": "Benoit Jacob", "email": "jacob.benoit.1@gmail.com", "time": "Wed Jun 17 04:05:39 2026 -0400" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Jun 17 10:05:39 2026 +0200" }, "message": "[Codegen][CPU] SelectUKernels for inner_tiled + --iree-llvmcpu-enable-llvm-ukernels. (#24569)\n\nWires the new C-bitcode ukernel framework into the LLVMCPU kernel-config\npipeline. Three pieces:\n\n* `LLVMCPUSelectUKernels.{h,cpp}` — when the target config has\n`llvm_ukernels \u003d \"inner_tiled\"`, `selectUKernel` matches\n`iree_codegen.inner_tiled` ops carrying a\n`#iree_cpu.data_tiled_mma_layout` and returns a `UKernelDescriptorAttr`\nwhose name is the corresponding `MMAIntrinsic` enum value lowercased\nwith the `iree_uk_mma_` prefix (e.g.\n`MMA_X86_AVX512BF16_1x16x2_F32_BF16` →\n`iree_uk_mma_x86_avx512bf16_1x16x2_f32_bf16`). One ukernel per\nintrinsic; `intrinsics_{m,n,k}` flow as function arguments and\nspecialize via bitcode LTO at the call site. Filters out `None` and the\n`MMA_GENERIC_*` family — neither has a corresponding ukernel.\n\n* `--iree-llvmcpu-enable-llvm-ukernels\u003d\u003ccsv\u003e` CL flag — bound to a new\n`LLVMTarget.llvmUkernels` field, serialized into the target config as\n`llvm_ukernels \u003d \"\u003ccsv\u003e\"`. Empty (the default) means off; passing\n`inner_tiled` opts dispatches into the new framework. The flag name\nleaves room for a future `mlir_ukernels`-style additional category (and\nfor now `inner_tiled` is also the only value). New helper\n`hasLlvmUkernel(config, category)` in Codegen/Utils — distinct from the\nexisting `hasUkernel` to keep the legacy mmt4d ukernels and the new\nLLVM-bitcode ukernels on independent enable flags.\n\n* `KernelDispatch.cpp::setRootConfig(InnerTiledOp)` — calls\n`selectUKernel` at the start and, on a match, sets the descriptor via\n`setUKernelDescriptor`. Tile sizes and translation_info are unchanged:\nthe ukernel substitutes for the *innermost* intrinsic execution only,\nthe surrounding tile sizes and pipeline still hold. Bitcode resolution\nis deferred to the `#iree_cpu.ukernel_provider` during\n`LowerBitcodeUKernelsPass`, matching the GPU split between \"match\"\n(here) and \"attach\" (provider).\n\nLit test (`select_ukernel.mlir`) runs\n`iree-llvmcpu-select-lowering-strategy` on two `inner_tiled` ops sharing\nthe same MMA intrinsic but differing in target config: the one with\n`llvm_ukernels \u003d \"inner_tiled\"` picks up the\n`iree_uk_mma_x86_avx512bf16_1x16x2_f32_bf16` descriptor; the other does\nnot, locking in the \"off by default\" property.\n\nProgress towards https://github.com/iree-org/iree/issues/24574.\n\nSigned-off-by: Benoit Jacob \u003cjacob.benoit.1@gmail.com\u003e\nCo-authored-by: Claude Opus 4.7 \u003cnoreply@anthropic.com\u003e" }, { "commit": "a67fb36f2bf9e866b10ab4503c0139e1cffec393", "tree": "87300461be652460866e2c27f7618efd451387fb", "parents": [ "a937cf9adc8886732970a849491bc35f6341f991" ], "author": { "name": "Benoit Jacob", "email": "jacob.benoit.1@gmail.com", "time": "Tue Jun 16 08:26:43 2026 -0400" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jun 16 14:26:43 2026 +0200" }, "message": "[Codegen][CPU] Register embedded ukernel bitcode + provider lookup. (#24568)\n\nWires the LLVMCPU plugin and the `#iree_cpu.ukernel_provider` attribute\nto actually resolve ukernel bitcode:\n\n* On plugin init, the embedded `iree_uk_cpu_bitcode` TOC is iterated and\neach `.bc` is added to the global `EmbeddedDataDirectory` (mirrors\n`addAMDGPUUkernelBitcodeToGlobalEmbeddedDataDirectory` in\n`ROCMTarget.cpp`).\n\n* `UKernelProviderAttr::createAndReplaceWithUkernelOp` now resolves the\nbitcode by name: user-supplied `hal.executable.objects` ancestors first\n(BYO and BYO-override paths), then the embedded directory. If found and\nnot already on the op, the attribute is attached to the source op; the\ndefault `LowerBitcodeUKernelsPass` rewrite then preserves it on the\nresulting `ukernel.generic`. The provider still returns `std::nullopt`\nfor the rewrite itself — specialized `inner_tiled` handling (scalar\n`intrinsics_{m,n,k}` + outer K count + ACC inner stride) lands with\nSelectUKernels in a follow-up.\n\n* Filename match is `\u003cukernelName\u003e.\u003cfeatures\u003e.bc` (or bare\n`\u003cukernelName\u003e.bc`), matching the build rules under\n`compiler/plugins/target/LLVMCPU/builtins/ukernel/`. Multi-variant\ndisambiguation by target feature set also lands with SelectUKernels.\n\nBUILD.bazel: LLVMCPU plugin gains a dep on\n\n`//compiler/plugins/target/LLVMCPU/builtins/ukernel:iree_uk_cpu_bitcode`,\nand the `iree_cpu` dialect picks up HAL IR + `EmbeddedDataDirectory` so\nthe provider implementation can live with the attribute (consistent with\nhow `ROCMUkernelBitcodeSupport.cpp` sits inside the ROCM dialect).\n\nTests: a three-way lit test (`lookup_builtin_and_byo.mlir`) covers each\nbranch of the lookup:\n1. Built-in only — no user objects; expect a `dense_resource\u003c…\u003e` with\nthe embedded bf16 bitcode (2732 bytes) attached.\n2. BYO override — user supplies bitcode under the built-in\u0027s filename;\nexpect the user\u0027s bytes to flow through unchanged (and CHECK-NOT against\n`dense_resource` to catch a regression where the provider silently swaps\nin the embedded copy).\n3. Pure BYO — user-only name with no matching built-in; expect the\nuser\u0027s bitcode to surface on the rewritten op.\n\nProgress towards https://github.com/iree-org/iree/issues/24574.\n\nSigned-off-by: Benoit Jacob \u003cjacob.benoit.1@gmail.com\u003e\nCo-authored-by: Claude Opus 4.7 \u003cnoreply@anthropic.com\u003e" }, { "commit": "a937cf9adc8886732970a849491bc35f6341f991", "tree": "b23c01f09828899cb65c45e80fe1b494192696aa", "parents": [ "3f2e10b7b787624a858d833112ab0798a1014bd0" ], "author": { "name": "Stefan Schuermans", "email": "schuermans@roofline.ai", "time": "Tue Jun 16 09:04:04 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jun 16 09:04:04 2026 +0200" }, "message": "Integrate LLVM to llvm/llvm-project@66e5a889c807 (#24606)\n\nAdd a fix for a use-after-free from\ne79e056ee982 [mlir][CSE] Remove the opsToErase container and immediately\ndelete dead ops. (#203702) (will be upstreamed to LLVM in parallel)\n\nSigned-off-by: Stefan Schuermans \u003cschuermans@roofline.ai\u003e" }, { "commit": "3f2e10b7b787624a858d833112ab0798a1014bd0", "tree": "f71ee517607638c54a83888a58e1a86d08115005", "parents": [ "f8d9ae71c890e5edf9eb81eccf0099f375a41d50" ], "author": { "name": "Michael Interlandi", "email": "43190101+Minterl@users.noreply.github.com", "time": "Mon Jun 15 14:41:06 2026 -0400" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jun 15 18:41:06 2026 +0000" }, "message": "[Fix][Build System] Include necessary header files in archive distrubution (#24596)\n\ncloses #24590 \n\nSome header files were listed as sources and vice versa.\n\nI took the liberty of rearranging more than just the one allocator.h, so\nif there\u0027s some context I should have been aware of I\u0027d be happy to\nrevert whatever necessary.\n\n---------\n\nSigned-off-by: Mike Interlandi \u003c43190101+Minterl@users.noreply.github.com\u003e" }, { "commit": "f8d9ae71c890e5edf9eb81eccf0099f375a41d50", "tree": "49038bc68a977c36980bc8feeefaabd85bf0f5bd", "parents": [ "521a8922ba4d3dc32b4df9424c293862a1caccaa" ], "author": { "name": "Ha-Eyz", "email": "eyilmez@roofline.ai", "time": "Mon Jun 15 14:34:47 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jun 15 12:34:47 2026 +0000" }, "message": "Inlcude absi in MathToVM Pattern and add testcases for it (#24592)\n\nWe have found some models, which failed to compile to vmvx, due to a\nmissing conversion for math.absi.\n\n#7080 already implemented vm.abs.i32 and vm.abs.i64 and included a\nGenericOpConversion in\n[VMToEmitC/ConvertVMToEmitC.cpp](https://github.com/iree-org/iree/blob/a9e91ecb68b23241349acfbb2ede00afa4c107b7/compiler/src/iree/compiler/Dialect/VM/Conversion/VMToEmitC/ConvertVMToEmitC.cpp#L5037-L5038)\n\nIt only requies a simple addition to the patterns in\nMathToVM/Patterns.cpp, for the models to successfully compile to vmvx. I\nalso expanded the tests in arithmetic_ops.mlir, to include a check for\nvm.abs.i32 and vm.abs.i64.\n\nSigned-off-by: Hakan Eyilmez \u003ceyilmez@roofline.ai\u003e\n\nSigned-off-by: default \u003ceyilmez@roofline.ai\u003e" }, { "commit": "521a8922ba4d3dc32b4df9424c293862a1caccaa", "tree": "a8a6cfa5ce1ef3d2a8a0cf4c2106bc6aa6749e89", "parents": [ "5d9eaeed92bbdd3102ba06e50686b5470df016c0" ], "author": { "name": "Roberto Laudani", "email": "laudani@roofline.ai", "time": "Fri Jun 12 10:44:53 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Jun 12 10:44:53 2026 +0200" }, "message": "Integrate LLVM to llvm/llvm-project@831ed97b1215 (#24603)\n\nCarries the FuncToEmitC Bazel-deps fix (add :IR and //llvm:Support),\nneeded by upstream 123078c21cfb.\n\nSigned-off-by: Roberto Laudani \u003claudani@roofline.ai\u003e" }, { "commit": "5d9eaeed92bbdd3102ba06e50686b5470df016c0", "tree": "d01fab5a06df376a9522758b99ba91ee817ef46b", "parents": [ "4495c739b3e5376aba933a8b402e225994b91b82" ], "author": { "name": "Benoit Jacob", "email": "jacob.benoit.1@gmail.com", "time": "Thu Jun 11 11:19:01 2026 -0400" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Jun 11 11:19:01 2026 -0400" }, "message": "[Codegen][CPU] Seed C-bitcode ukernel framework with bf16 and i8 seeds. (#24567)\n\nAdds compiler/plugins/target/LLVMCPU/builtins/ukernel/, the new home for\nLLVMCPU-only C microkernels. Modelled after the ROCM C ukernel framework\n(compiler/plugins/target/ROCM/builtins/ukernel/): compile each ukernel\nto LLVM bitcode, embed those .bc files into iree-compile, and emit them\nas self-contained `hal.executable_object`s on dispatch variants —\ndistinct from the legacy mmt4d ukernels under runtime/, which serve a\nnow-defunct VMVX path and are built twice.\n\nThis first commit lands the scaffolding plus two inner-K-loop seeds with\nstub bodies (filled in by a later commit):\n* `iree_uk_mma_x86_avx512bf16_1x16x2_f32_bf16.c` (bf16 x bf16 -\u003e f32)\nand `iree_uk_mma_x86_avx512vnni_16x16x2_i32_i8_casti16.c` (i8 x i8 -\u003e\ni32 via VNNI), plus `common.h` (no-stdlib stdint replacements);\n* `iree_bitcode_library` + `iree_c_embed_data` rules, driven by a\n`(stem, features, copts)` table so adding a seed is one row (CMake\nregenerated; `iree_bitcode_library` in `bazel_to_cmake_converter.py`\nextended to forward `out`, so the embedded filename is\n`\u003cname\u003e.\u003carch\u003e_\u003cfeatures\u003e.bc`);\n* a `README.md` design doc covering scope, build, IR representation,\nend-to-end flow, and authoring/test guidance;\n* `#iree_cpu.ukernel_provider`, the CPU analogue of\n`#rocm.ukernel_provider`, declared in `IREECPUAttrs.td`/`.cpp` with a\n`createAndReplaceWithUkernelOp` that currently delegates to the default\n`LowerBitcodeUKernelsPass` fallback. Specialized `inner_tiled` handling\n(threading `intrinsics_{m,n,k}` and the outer K count) will land in a\nfollow-up alongside `SelectUKernels` and pipeline integration.\n\nTests:\n* roundtrip lit test for the new `#iree_cpu.ukernel_provider` attribute;\n* lit tests running `--iree-codegen-lower-bitcode-ukernels` on ops\ncarrying both `iree_codegen.ukernel \u003d \"...\"` and a user-supplied\n`hal.executable.objects` bitcode (one per seed), asserting they are\nrewritten to `iree_codegen.ukernel.generic` with the bitcode preserved.\n\nProgress towards https://github.com/iree-org/iree/issues/24574.\n\n---------\n\nSigned-off-by: Benoit Jacob \u003cjacob.benoit.1@gmail.com\u003e\nCo-authored-by: Claude Opus 4.8 (1M context) \u003cnoreply@anthropic.com\u003e" }, { "commit": "4495c739b3e5376aba933a8b402e225994b91b82", "tree": "b6dc2e70023a1693dd237b9a6b2f9f62453d5e61", "parents": [ "196c18af0755370c62eb0398dcff8a746bc358e5" ], "author": { "name": "Tobias Fuchs", "email": "9053039+devtbi@users.noreply.github.com", "time": "Thu Jun 11 16:15:11 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Jun 11 16:15:11 2026 +0200" }, "message": "[SPIRV] Add target-feature cli option (#24598)\n\nAllow manually specifying `vulkan-target-features` to overwrite the\ntarget defaults in `VulkanSPIRVTarget.cpp` (e.g. for testing, newly\nsupported features).\n\nSigned-off-by: Tobias Fuchs \u003cfuchs@roofline.ai\u003e" }, { "commit": "196c18af0755370c62eb0398dcff8a746bc358e5", "tree": "73eae08c11bbd2e70f0f18ce5b36f980435c9bff", "parents": [ "85a352faaef9a3b4e10cf9f9ad3b8559ed82f1bd" ], "author": { "name": "Rechie Kho", "email": "50512341+RechieKho@users.noreply.github.com", "time": "Thu Jun 11 18:08:54 2026 +0800" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Jun 11 12:08:54 2026 +0200" }, "message": "[Runtime] Align `iree_async_posix_worker_t` (#24589)\n\nFix #24578\n\nThe fix includes aligning `iree_async_posix_worker_t` to\n`iree_hardware_constructive_interference_size`.\n\nPertaining to the concern of possible improper offset via pointer\ncasting mentioned in this\n[comment](https://github.com/iree-org/iree/issues/24578#issuecomment-4646834986)\n, it comes from line 179 in file\n`runtime\\src\\iree\\async\\platform\\posix\\proactor.c`:\n```cpp\n // Set up pointers into trailing data.\n proactor-\u003eworkers \u003d\n (iree_async_posix_worker_t*)((uint8_t*)proactor + workers_offset); // \u003c- This\n proactor-\u003eworker_count \u003d worker_count;\n```\n\nThe worker offset is calculated from line 148 in the same file:\n```cpp\n IREE_RETURN_AND_END_ZONE_IF_ERROR(\n z0, IREE_STRUCT_LAYOUT(\n sizeof(iree_async_proactor_posix_t), \u0026total_size,\n IREE_STRUCT_FIELD_ALIGNED(\n worker_count, iree_async_posix_worker_t,\n iree_hardware_destructive_interference_size, \u0026workers_offset), // \u003c- This\n IREE_STRUCT_FIELD_ALIGNED(\n ready_pool_capacity, iree_async_posix_ready_op_t,\n iree_hardware_destructive_interference_size,\n \u0026ready_entries_offset),\n IREE_STRUCT_FIELD(completion_pool_capacity,\n iree_async_posix_completion_t,\n \u0026completion_entries_offset),\n IREE_STRUCT_FIELD(message_pool_capacity,\n iree_async_message_pool_entry_t,\n \u0026message_entries_offset)))\n```\n\nFrom what I read, `IREE_STRUCT_FIELD_ALIGNED` considers the alignment. I\nsupposed the offset calculation should be correct, especially with the\nalignment to be the same.\n\nMoreover, I\u0027ve also saw some manual padding in the struct via\n`_padding`. I remove such padding as I suppose the alignment will pad\nfor us.\n\n---------\n\nSigned-off-by: Rechie Kho \u003c50512341+RechieKho@users.noreply.github.com\u003e" }, { "commit": "85a352faaef9a3b4e10cf9f9ad3b8559ed82f1bd", "tree": "d35cb5328d2c2d2761741ff2229555a02bce863e", "parents": [ "8c4631e905e19cc430d4e1ab84023e85bb265464" ], "author": { "name": "Stefan Schuermans", "email": "schuermans@roofline.ai", "time": "Thu Jun 11 10:55:16 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Jun 11 08:55:16 2026 +0000" }, "message": "Integrate LLVM to llvm/llvm-project@696f4d562847 (#24599)\n\nAdapted usage of TensorType to TensorLikeType and similar types required\nby: 696f4d562847 [AMDGPU] Fix immediate parsing for packed types\n(#202417)\n\nSigned-off-by: Stefan Schuermans \u003cschuermans@roofline.ai\u003e" }, { "commit": "8c4631e905e19cc430d4e1ab84023e85bb265464", "tree": "de33680546401cf6b825360e2e7d335b34523613", "parents": [ "964b7ad2b97527406b6d2f97e5bb49d2c7312329" ], "author": { "name": "Artem Gindinson", "email": "gindinson@roofline.ai", "time": "Thu Jun 11 09:02:35 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Jun 11 09:02:35 2026 +0200" }, "message": "[SPIRV][GPU] Add Mali G720 and other Arm 5 Gen target details (#24595)\n\nBased on the official `vulkaninfo`, define `arm5gen` as an IREE Vulkan\ntarget for devices such as Mali G720 Immortalis. Include all compute\nbitwidths into the declaration, based on the official support for\n`shaderInt64` capability - besides, initial experiments on a set of\nTorch and TFLite models have shown that Arm driver emulation for wide\nintegers holds up against the current emulation in IREE.\n\nSigned-off-by: Artem Gindinson \u003cgindinson@roofline.ai\u003e" }, { "commit": "964b7ad2b97527406b6d2f97e5bb49d2c7312329", "tree": "68404a243135ee0051a50c133ee5d9071e5e9785", "parents": [ "9550dfb3d2d2e6fbe3708fe6b4a6a1a8600d595b" ], "author": { "name": "Tobias Fuchs", "email": "9053039+devtbi@users.noreply.github.com", "time": "Wed Jun 10 14:49:11 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Jun 10 14:49:11 2026 +0200" }, "message": "[HAL] Add missing bufferUsage for Mapping in tryAddSharedUsageBits (#24549)\n\n- Map persistently to support sharing via export/import.\n- Persistent mapping in turn requires host-visible memory.\n\nSigned-off-by: Tobias Fuchs \u003cfuchs@roofline.ai\u003e" }, { "commit": "9550dfb3d2d2e6fbe3708fe6b4a6a1a8600d595b", "tree": "bad55a476a399e4e8a2d210c4e2f1236968fefb7", "parents": [ "c39608796967953f8edc2c1a4cfd03d4888b3bbd" ], "author": { "name": "Artem Gindinson", "email": "gindinson@roofline.ai", "time": "Wed Jun 10 12:11:51 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Jun 10 10:11:51 2026 +0000" }, "message": "[Vulkan][SPIRV] Add initial LIT for known Vulkan target features (Arm GPUs)\n\nCreate a regression test for Arm Mali targets, similar to CUDA/ROCM\ntests for recorded target capabilities. This can be later expanded for\nall known Vulkan targets within IREE.\n\nAdditionally, fix the lexeme for Mali G78.\n\n\nAssisted-by: Codex \u003cnoreply@openai.com\u003e\n\nSigned-off-by: Artem Gindinson \u003cgindinson@roofline.ai\u003e" }, { "commit": "c39608796967953f8edc2c1a4cfd03d4888b3bbd", "tree": "ec814b8cce609c218ab55f5e6fd0637da3f154cb", "parents": [ "5c799b6962679b69c4265ff039e6cc6b0fa5fa51" ], "author": { "name": "Ege Beysel", "email": "beysel@roofline.ai", "time": "Wed Jun 10 10:53:32 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Jun 10 10:53:32 2026 +0200" }, "message": "[Doc] Update YouTube channel link in README (#24597)\n\nIREE Youtube channel link was wrong/outdated, this fixes it." }, { "commit": "5c799b6962679b69c4265ff039e6cc6b0fa5fa51", "tree": "9e46d8d289b9228d8cd980e80bf5903bc962fe9b", "parents": [ "694721478f5dfd40ef51a0bdeccc4c5cc1882928" ], "author": { "name": "Florian Walbroel", "email": "walbroel@roofline.ai", "time": "Wed Jun 10 10:41:26 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Jun 10 08:41:26 2026 +0000" }, "message": "[Runtime] Unify dtype handling in Python bindings (#24587)\n\nSigned-off-by: Florian Walbroel \u003cwalbroel@roofline.ai\u003e" }, { "commit": "694721478f5dfd40ef51a0bdeccc4c5cc1882928", "tree": "891387cad868d023e231df408595c639d54fd530", "parents": [ "8365d65a74d836df504e978397ca2a3f9ce24827" ], "author": { "name": "Stefan Schuermans", "email": "schuermans@roofline.ai", "time": "Wed Jun 10 08:08:43 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Jun 10 08:08:43 2026 +0200" }, "message": "Integrate LLVM to llvm/llvm-project@917117ceeebf (#24588)\n\nDrop getEmptyKey() and getTombstoneKey() for DenseMapInfo-related\nclasses. The reason is that LLVM dropped those in:\n1e3dc606df3a [DenseMap] Store occupancy in a packed used-bit array\n(#201281) 1f10f1ca8af3 [DenseMap] Replace tombstone deletion with TAOCP\n6.4 Algorithm R (#200595)\n\nDropping this was also needed in stablehlo and torch-mlir. Those\nsubmodules are updated here as well.\n\nIn ROCM mlir_ukernels, the syntax of \"rocdl.sched.barrier\" had to be\nadapted to use \"none\" instead of \"0\".\nFurthermore, it now prints the keyword without brackets.\n681fc74ac47e [mlir][ROCDL] Move ROCDL intrinsic enum immargs to enums\n(#198875)\n \nRanked-tensor type-constraint description gained \"non-token\"\n67aaa03dac58 [mlir][IR] Add builtin `TokenType` (#195640)\n \nemitc.call_opaque prints args/template_args as properties \u003c{...}\u003e\n8f58a4cab3a7 [mlir][emitc]: Add MemberCallOpaque op (#200057)\n \ncmpi+select clamp idioms fold to arith.minsi/arith.maxsi\ne26ef0c94341 [mlir][arith] Canonicalize cmpi select to min/max (#201737)\n\nSigned-off-by: Stefan Schuermans \u003cschuermans@roofline.ai\u003e" }, { "commit": "8365d65a74d836df504e978397ca2a3f9ce24827", "tree": "99b5a8706b1ef315191ed7ea195a225dcbbb66c7", "parents": [ "f6395fd2b519db00f36d2b19360e19eba597107b" ], "author": { "name": "Benoit Jacob", "email": "jacob.benoit.1@gmail.com", "time": "Tue Jun 09 12:33:28 2026 -0400" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jun 09 12:33:28 2026 -0400" }, "message": "[Codegen][CPU] Rename LLVMCPU/Builtins -\u003e builtins to mirror GPU plugin layout. (#24586)\n\nThe GPU target plugin keeps all embedded-bitcode builtins under a single\nlowercase `builtins/` directory (compiler/plugins/target/ROCM/builtins/,\nwith `ukernel/`, `mlir_ukernel/`, ... as subdirs). LLVMCPU instead had a\ncapital `Builtins/`. That capital directory collides, on\ncase-insensitive filesystems (Windows, macOS), with a new lowercase\n`builtins/` we want to add for the LLVMCPU C-ukernel framework -- the\ncollision clobbers the CMake `Builtins` target and breaks the MSVC\nbuild. Lowercase the directory to match the GPU plugin layout and make\nroom for `builtins/ukernel/`.\n\nPure directory rename plus include-path / dep / generated-CMake updates;\nno functional change.\n\nProgress towards https://github.com/iree-org/iree/issues/24574.\n\nSigned-off-by: Benoit Jacob \u003cjacob.benoit.1@gmail.com\u003e\nCo-authored-by: Claude Opus 4.8 (1M context) \u003cnoreply@anthropic.com\u003e" }, { "commit": "f6395fd2b519db00f36d2b19360e19eba597107b", "tree": "b801033ec574ba18caa8e894a52b950639f63d81", "parents": [ "a9e91ecb68b23241349acfbb2ede00afa4c107b7" ], "author": { "name": "Ege Beysel", "email": "beyselege@gmail.com", "time": "Tue Jun 09 18:30:50 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jun 09 18:30:50 2026 +0200" }, "message": "fix(CI): long-running emulated rv64 matmul integration tests (#24593)\n\nThe RISCV-64 e2e matmul integration tests without the ukernels are very\nlong-running under QEMU emulation, and were causing timeouts in CI. This\nPR disables the generic (non-uk) vectorization path for those tests\nuntil we properly support codegen.\n\n(Claude-generated summary)\n\n## Summary\n\nThe RISC-V 64 e2e matmul integration tests that run **without ukernels**\n(`--iree-opt-data-tiling --iree-llvmcpu-enable-ukernels\u003dnone`) are\nextremely\nslow under QEMU and were timing out CI (60 s per-test limit). This PR\nadds\n`noriscv` to all non-ukernel `dt`/`experimental_dt` matmul variants,\nsince the\ngeneric vectorization path for data-tiled matmul is not yet properly\nsupported\non RISC-V — only the ukernel path is validated there.\n\n**Why it\u0027s slow:** with data-tiling on but ukernels off, the packed\n`mmt4d` is\nlowered through generic vectorization. For the wide `M0×N0` tile it\nselects\n(`N0 \u003d VLEN/8`, `M0 \u003d 7`), the widening multiply-accumulate has no\nvector×scalar\nform, so the inner loop rebuilds the LHS broadcast every K-step via a\nstorm of\n`vsetvli` reconfigurations and `vrgather`/`vslideup` permutes — e.g. for\ni8 at\nVLEN\u003d256, ~118 `vsetvli` + ~19 `vrgather` per dispatch, vs ~2 `vsetvli`\nand no\ngathers for the ukernel. QEMU emulates every vector instruction\nelement-by-element, and `vsetvli`/`vrgather`/`vslide` are among the\ncostliest to\nemulate, so the full shape set runs for tens of seconds and trips the\ntimeout.\n`dt_i8_i32` and `experimental_dt_i8_i32` hit it first; `dt_f32_f32` was\nalready\nat ~52 s (one slow runner from flaking).\n\nFailing CI run:\nhttps://github.com/iree-org/iree/actions/runs/27192246864/job/80276315195\n\n**Emulation vs. real hardware:** the timeout is largely a QEMU artifact.\nOn a\nSpaceMiT X60 (VLEN\u003d256, native), the heaviest shape (540×332×516) runs\nin\nmilliseconds — but the generic path is still 3.5–6× slower than the\nukernel\npath, confirming it exercises an unsupported/unoptimized path rather\nthan just\nan emulator quirk:\n\n| variant (540×332×516) | 1 thread | 8 threads | generic ÷ ukernel |\n|---|---|---|---|\n| i8 generic | 123 ms | 37.9 ms | **6.1×** |\n| i8 ukernel | 20.3 ms | 6.15 ms | — |\n| f32 generic | 108 ms | 29.1 ms | **3.5×** |\n| f32 ukernel | 30.9 ms | 9.08 ms | — |\n\n(The gap is specific to the wide-`M0` tile; narrow-M shapes pick `M0\u003d1`,\nemit\nclean `vwmacc.vx`, and are ~1.3×.)\n\n\nAssisted-by: Claude Code\n\n---------\n\nSigned-off-by: Ege Beysel \u003cbeyselege@gmail.com\u003e" }, { "commit": "a9e91ecb68b23241349acfbb2ede00afa4c107b7", "tree": "2184ecf847f3902e0b389ccd909d5216de49dfa3", "parents": [ "b32ca40857b9e91ed99f91ba86a730a1feb9ff49" ], "author": { "name": "WMC", "email": "tnwilly@gmail.com", "time": "Tue Jun 09 14:35:50 2026 +0800" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Tue Jun 09 08:35:50 2026 +0200" }, "message": "[LLVMGPU] Add sm_120 TileAndFuse config coverage, consolidate MMA sync pipeline tests (#24577)\n\n## Description\nAdds LLVMGPU TileAndFuse config-selection coverage for the CUDA `sm_120`\ntarget and consolidates MMA sync pipeline-lowering coverage across\nNVIDIA\nGPU architectures.\n\nThe `sm_120` config-selection test verifies that f16 matmul cases select\nthe\nNVIDIA MMA TileAndFuse path before any architecture-specific tuning is\nintroduced. The pipeline-lowering tests are kept target-independent\nbecause\nthey start from IR with an attached `mma_sync` intrinsic and only verify\nthat\nthe selected lowering pipeline generates the corresponding\n`nvgpu.mma.sync`\nops.\n\nCovered `sm_120` config-selection cases:\n- `f16xf16 -\u003e f32` matmul selects TileAndFuse with `NV_MMA_SYNC`\n- `f16xf16 -\u003e f16` matmul selects TileAndFuse with `NV_MMA_SYNC`\n- `f16xf16 -\u003e f32` matmul accumulate sets `convert_acc_gemm`\n\nCovered target-independent pipeline-lowering cases:\n- `f16xf16 -\u003e f32` TileAndFuse lowering generates `nvgpu.mma.sync`\n- `f16xf16 -\u003e f16` TileAndFuse lowering generates `nvgpu.mma.sync`\n- `f16xf16 -\u003e f32` VectorDistribute lowering generates `nvgpu.mma.sync`\n- `f16xf16 -\u003e f16` VectorDistribute lowering generates `nvgpu.mma.sync`\n\nThis is baseline regression coverage only; it does not introduce new\ntile\nheuristics or `sm_120`-specific tuning.\n\n## Test\n- `llvm-lit -v \\\n\ncompiler/src/iree/compiler/Codegen/LLVMGPU/test/NVVM/config_tile_and_fuse_sm120.mlir\n\\\n\ncompiler/src/iree/compiler/Codegen/LLVMGPU/test/NVVM/config_tile_and_fuse_sm80.mlir\n\\\n\ncompiler/src/iree/compiler/Codegen/LLVMGPU/test/NVVM/pipeline_tile_and_fuse_mma_sync.mlir\n\\\n\ncompiler/src/iree/compiler/Codegen/LLVMGPU/test/NVVM/pipeline_vector_distribute_mma_sync.mlir`\n\n\n```\n-- Testing: 4 tests, 4 workers --\nPASS: IREE :: src/iree/compiler/Codegen/LLVMGPU/test/NVVM/config_tile_and_fuse_sm120.mlir (1 of 4)\nPASS: IREE :: src/iree/compiler/Codegen/LLVMGPU/test/NVVM/config_tile_and_fuse_sm80.mlir (2 of 4)\nPASS: IREE :: src/iree/compiler/Codegen/LLVMGPU/test/NVVM/pipeline_vector_distribute_mma_sync.mlir (3 of 4)\nPASS: IREE :: src/iree/compiler/Codegen/LLVMGPU/test/NVVM/pipeline_tile_and_fuse_mma_sync.mlir (4 of 4)\n\nTesting Time: 0.14s\n\nTotal Discovered Tests: 4\n Passed: 4 (100.00%)\n```\n\n---------\n\nSigned-off-by: weimin023 \u003ctnwilly@gmail.com\u003e" }, { "commit": "b32ca40857b9e91ed99f91ba86a730a1feb9ff49", "tree": "10d2eefc803e9fcd7167f31ba6490362d5dac7e8", "parents": [ "c1c962b63cd248f1c7b6d9a9ac8288a57d711c46" ], "author": { "name": "Agustin Nahuel Coppari Hollmann", "email": "70057799+copparihollmann@users.noreply.github.com", "time": "Mon Jun 08 01:24:40 2026 -0700" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Mon Jun 08 10:24:40 2026 +0200" }, "message": "[LLVMCPU][RISCV] Add RVV int8 vector-contract custom kernels for widening i8*i8-\u003ei32 matmul (#23734)\n\nFixes iree-org/iree#23730\n\nThis PR adds RVV custom vector-contract kernel support for widening\ni8*i8-\u003ei32 matmul on RISC-V.\n\nIt updates:\n- CPU encoding tile enumeration for RVV int8-\u003ei32 matmul\n- LLVMCPU kernel dispatch RVV vector sizes\n- VectorContractCustomKernels with an RVV intrinsic-based int8 path\n- lit tests for vector-contract custom kernels and mmt4d vector lowering\n\nSomething I would like some feedback on is what would be your preferred\nway to test this e2e. So far I compile it and run it on the Banana-pi\nSpacemiT X60.\n\nAssisted-by: ChatGPT\n\n---------\n\nSigned-off-by: Agustin N. Coppari Hollmann \u003ccopparihollmann@gmail.com\u003e" }, { "commit": "c1c962b63cd248f1c7b6d9a9ac8288a57d711c46", "tree": "605bb92cc9c09c893de5bfc2d7ae1504590b1215", "parents": [ "c6753332aa7781e7813b87118173a04911366b76" ], "author": { "name": "Benoit Jacob", "email": "jacob.benoit.1@gmail.com", "time": "Fri Jun 05 14:51:29 2026 -0400" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Jun 05 14:51:29 2026 -0400" }, "message": "[Codegen][CPU] Fold reshapes into map_store per reassociation group. (#24535)\n\n`foldReshapeIntoMapStore` composed an expand/collapse reshape into a\n`map_store`\u0027s index transformation via one global `linearize` over the\nsource shape plus `delinearize` over the result shape. Under dynamic\nshapes that `delinearize` lowers to a dynamic integer division per\nelement.\n\nFold each reassociation group independently instead: an `expand_shape`\nsplits one source index by just that group\u0027s result sizes; a\n`collapse_shape` merges one group of source indices. The split/merge\nfactors are then per-group -- typically static tile sizes -- so the\nscalarized transformation is static shifts/masks with no per-element\ndivision.\n\nSpeeds up the i8 data-tiled matmul\u0027s C-encode dispatch; i8 inner_tiled\nmatmul, 4096x4096 on Zen 4: 52.9ms -\u003e 46.9ms.\n\nAlso document, at `MapStoreOpVectorizationModel::isVectorizable`, why a\nCPU-tiled `map_store` reaches the vectorizer dynamically shaped and\nscalarizes -- which is precisely what makes this per-group,\ndivision-free fold matter -- while the same op vectorizes on GPU.\nComment only, no behavior change.\n\nProgress towards #24515.\n\nSigned-off-by: Benoit Jacob \u003cjacob.benoit.1@gmail.com\u003e\nCo-authored-by: Claude Opus 4.7 \u003cnoreply@anthropic.com\u003e" }, { "commit": "c6753332aa7781e7813b87118173a04911366b76", "tree": "d82c9a0112a338c5a348ceb718a3218c6a800a8b", "parents": [ "d4ee61f436bcc95c1d113e2854ec9352def29dda" ], "author": { "name": "Benoit Jacob", "email": "jacob.benoit.1@gmail.com", "time": "Fri Jun 05 12:20:37 2026 -0400" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Jun 05 12:20:37 2026 -0400" }, "message": "[Codegen][CPU] Add x86 AVX-512 VNNI 16x16x2 i8 MMA intrinsic. (#24534)\n\n`MMA_X86_AVX512VNNI_16x16x2_I32_I8_CASTI16` processes a full 16x16x2 i8\nmatmul tile, mirroring the mmt4d ukernel\u0027s hot loop. Unlike the 1x16x2 /\n16x1x2 CASTI16 variants -- one row per intrinsic, with a per-row i8-\u003ei16\nwiden + broadcast -- it consumes whole 16x2 i8 panels: one `vpmovsxbw`\nwiden per panel, 4 in-lane + 4 128-bit-block shuffles to fan the panels\nacross a 4x4 grid, then 16 `vpdpwssd`. The 16x16 accumulator uses a\nblock-interleaved `TileSwizzle` so each `vpdpwssd` accumulator is a\ncontiguous register.\n\ni8 inner_tiled matmul, 4096x4096 on Zen 4: 72.5ms -\u003e 52.9ms.\n\nProgress towards #24515.\n\n---------\n\nSigned-off-by: Benoit Jacob \u003cjacob.benoit.1@gmail.com\u003e\nCo-authored-by: Claude Opus 4.7 \u003cnoreply@anthropic.com\u003e" }, { "commit": "d4ee61f436bcc95c1d113e2854ec9352def29dda", "tree": "f911ae322856010165d9924bc6598bc73c5cfa5d", "parents": [ "4bced6946652ec77a49919b0b0a2ffad93a87b39" ], "author": { "name": "Benoit Jacob", "email": "jacob.benoit.1@gmail.com", "time": "Fri Jun 05 12:20:24 2026 -0400" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Fri Jun 05 12:20:24 2026 -0400" }, "message": "[Codegen][CPU] Fold reshape-containing encoding relayouts to map_store. (#24533)\n\nGPU\u0027s configuration pipeline folds the `pack`/`expand_shape`/`transpose`\nrelayout chain from encoding materialization into a single\n`iree_linalg_ext.map_store` before tiling; CPU did not. For a non-row-\nmajor encoding swizzle the intervening `tensor.expand_shape` (not a\n`TilingInterface` op) blocks producer fusion and strands an untiled,\nwhole-tensor `pack` intermediate.\n\nMirror GPU on CPU:\n- Add `RelayoutCombinationScope::DispatchReshape`: like `Dispatch` but\nrestricted to chains whose backward slice contains an\nexpand/collapse_shape. Pure pack/unpack/transpose chains tile fine and\nare left alone.\n- Run `CombineResultLayoutTransformation` with that scope in the CPU\nconfiguration pipeline, after MaterializeDeviceEncoding.\n- Skip `map_load`/`map_store` as `getRootOperation` candidates, so a\ndispatch with a real compute op plus a `map_store` roots on the compute\nop.\n\nInert for existing (row-major) CPU encodings.\n\nProgress towards #24515.\n\nSigned-off-by: Benoit Jacob \u003cjacob.benoit.1@gmail.com\u003e\nCo-authored-by: Claude Opus 4.7 \u003cnoreply@anthropic.com\u003e" }, { "commit": "4bced6946652ec77a49919b0b0a2ffad93a87b39", "tree": "dbed8666b75759ae4b0784855c162441d7d5480a", "parents": [ "9dd025b3f38df8c5e5ed4f7df89cafe28f2fdae0" ], "author": { "name": "Florian Walbroel", "email": "walbroel@roofline.ai", "time": "Wed Jun 03 22:10:03 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Jun 03 22:10:03 2026 +0200" }, "message": "[Runtime][Python] Add pyright checks and fix errors (#24561)\n\nSigned-off-by: Florian Walbroel \u003cwalbroel@roofline.ai\u003e" }, { "commit": "9dd025b3f38df8c5e5ed4f7df89cafe28f2fdae0", "tree": "172569e18ff42e1d944207aee7894c46db7b04a3", "parents": [ "37b8c2c1a1a33ca186217a49adbec09035d2772d" ], "author": { "name": "dependabot[bot]", "email": "49699333+dependabot[bot]@users.noreply.github.com", "time": "Wed Jun 03 15:51:53 2026 +0000" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Jun 03 15:51:53 2026 +0000" }, "message": "Bump actions/checkout from 6.0.2 to 6.0.3 in the github-actions group (#24563)\n\nBumps the github-actions group with 1 update:\n[actions/checkout](https://github.com/actions/checkout).\n\nUpdates `actions/checkout` from 6.0.2 to 6.0.3\n\u003cdetails\u003e\n\u003csummary\u003eRelease notes\u003c/summary\u003e\n\u003cp\u003e\u003cem\u003eSourced from \u003ca\nhref\u003d\"https://github.com/actions/checkout/releases\"\u003eactions/checkout\u0027s\nreleases\u003c/a\u003e.\u003c/em\u003e\u003c/p\u003e\n\u003cblockquote\u003e\n\u003ch2\u003ev6.0.3\u003c/h2\u003e\n\u003ch2\u003eWhat\u0027s Changed\u003c/h2\u003e\n\u003cul\u003e\n\u003cli\u003eUpdate changelog by \u003ca\nhref\u003d\"https://github.com/ericsciple\"\u003e\u003ccode\u003e@​ericsciple\u003c/code\u003e\u003c/a\u003e in \u003ca\nhref\u003d\"https://redirect.github.com/actions/checkout/pull/2357\"\u003eactions/checkout#2357\u003c/a\u003e\u003c/li\u003e\n\u003cli\u003efix: expand merge commit SHA regex and add SHA-256 test cases by \u003ca\nhref\u003d\"https://github.com/yaananth\"\u003e\u003ccode\u003e@​yaananth\u003c/code\u003e\u003c/a\u003e in \u003ca\nhref\u003d\"https://redirect.github.com/actions/checkout/pull/2414\"\u003eactions/checkout#2414\u003c/a\u003e\u003c/li\u003e\n\u003cli\u003eFix checkout init for SHA-256 repositories by \u003ca\nhref\u003d\"https://github.com/yaananth\"\u003e\u003ccode\u003e@​yaananth\u003c/code\u003e\u003c/a\u003e in \u003ca\nhref\u003d\"https://redirect.github.com/actions/checkout/pull/2439\"\u003eactions/checkout#2439\u003c/a\u003e\u003c/li\u003e\n\u003cli\u003eUpdate changelog for v6.0.3 by \u003ca\nhref\u003d\"https://github.com/yaananth\"\u003e\u003ccode\u003e@​yaananth\u003c/code\u003e\u003c/a\u003e in \u003ca\nhref\u003d\"https://redirect.github.com/actions/checkout/pull/2446\"\u003eactions/checkout#2446\u003c/a\u003e\u003c/li\u003e\n\u003c/ul\u003e\n\u003ch2\u003eNew Contributors\u003c/h2\u003e\n\u003cul\u003e\n\u003cli\u003e\u003ca href\u003d\"https://github.com/yaananth\"\u003e\u003ccode\u003e@​yaananth\u003c/code\u003e\u003c/a\u003e\nmade their first contribution in \u003ca\nhref\u003d\"https://redirect.github.com/actions/checkout/pull/2414\"\u003eactions/checkout#2414\u003c/a\u003e\u003c/li\u003e\n\u003c/ul\u003e\n\u003cp\u003e\u003cstrong\u003eFull Changelog\u003c/strong\u003e: \u003ca\nhref\u003d\"https://github.com/actions/checkout/compare/v6...v6.0.3\"\u003ehttps://github.com/actions/checkout/compare/v6...v6.0.3\u003c/a\u003e\u003c/p\u003e\n\u003c/blockquote\u003e\n\u003c/details\u003e\n\u003cdetails\u003e\n\u003csummary\u003eChangelog\u003c/summary\u003e\n\u003cp\u003e\u003cem\u003eSourced from \u003ca\nhref\u003d\"https://github.com/actions/checkout/blob/main/CHANGELOG.md\"\u003eactions/checkout\u0027s\nchangelog\u003c/a\u003e.\u003c/em\u003e\u003c/p\u003e\n\u003cblockquote\u003e\n\u003ch1\u003eChangelog\u003c/h1\u003e\n\u003ch2\u003ev6.0.3\u003c/h2\u003e\n\u003cul\u003e\n\u003cli\u003eFix checkout init for SHA-256 repositories by \u003ca\nhref\u003d\"https://github.com/yaananth\"\u003e\u003ccode\u003e@​yaananth\u003c/code\u003e\u003c/a\u003e in \u003ca\nhref\u003d\"https://redirect.github.com/actions/checkout/pull/2439\"\u003eactions/checkout#2439\u003c/a\u003e\u003c/li\u003e\n\u003cli\u003efix: expand merge commit SHA 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\u003ca\nhref\u003d\"https://github.com/TingluoHuang\"\u003e\u003ccode\u003e@​TingluoHuang\u003c/code\u003e\u003c/a\u003e\nin \u003ca\nhref\u003d\"https://redirect.github.com/actions/checkout/pull/2224\"\u003eactions/checkout#2224\u003c/a\u003e\u003c/li\u003e\n\u003cli\u003eUpdate package dependencies by \u003ca\nhref\u003d\"https://github.com/salmanmkc\"\u003e\u003ccode\u003e@​salmanmkc\u003c/code\u003e\u003c/a\u003e in \u003ca\nhref\u003d\"https://redirect.github.com/actions/checkout/pull/2236\"\u003eactions/checkout#2236\u003c/a\u003e\u003c/li\u003e\n\u003c/ul\u003e\n\u003ch2\u003ev4.2.2\u003c/h2\u003e\n\u003cul\u003e\n\u003cli\u003e\u003ccode\u003eurl-helper.ts\u003c/code\u003e now leverages well-known environment\nvariables by \u003ca href\u003d\"https://github.com/jww3\"\u003e\u003ccode\u003e@​jww3\u003c/code\u003e\u003c/a\u003e\nin \u003ca\nhref\u003d\"https://redirect.github.com/actions/checkout/pull/1941\"\u003eactions/checkout#1941\u003c/a\u003e\u003c/li\u003e\n\u003cli\u003eExpand unit test coverage for \u003ccode\u003eisGhes\u003c/code\u003e by \u003ca\nhref\u003d\"https://github.com/jww3\"\u003e\u003ccode\u003e@​jww3\u003c/code\u003e\u003c/a\u003e in \u003ca\nhref\u003d\"https://redirect.github.com/actions/checkout/pull/1946\"\u003eactions/checkout#1946\u003c/a\u003e\u003c/li\u003e\n\u003c/ul\u003e\n\u003ch2\u003ev4.2.1\u003c/h2\u003e\n\u003cul\u003e\n\u003cli\u003eCheck out other refs/* by commit if provided, fall back to ref by \u003ca\nhref\u003d\"https://github.com/orhantoy\"\u003e\u003ccode\u003e@​orhantoy\u003c/code\u003e\u003c/a\u003e in \u003ca\nhref\u003d\"https://redirect.github.com/actions/checkout/pull/1924\"\u003eactions/checkout#1924\u003c/a\u003e\u003c/li\u003e\n\u003c/ul\u003e\n\u003ch2\u003ev4.2.0\u003c/h2\u003e\n\u003cul\u003e\n\u003cli\u003eAdd Ref and Commit outputs by \u003ca\nhref\u003d\"https://github.com/lucacome\"\u003e\u003ccode\u003e@​lucacome\u003c/code\u003e\u003c/a\u003e in \u003ca\nhref\u003d\"https://redirect.github.com/actions/checkout/pull/1180\"\u003eactions/checkout#1180\u003c/a\u003e\u003c/li\u003e\n\u003cli\u003eDependency updates by \u003ca\nhref\u003d\"https://github.com/dependabot\"\u003e\u003ccode\u003e@​dependabot\u003c/code\u003e\u003c/a\u003e- \u003ca\nhref\u003d\"https://redirect.github.com/actions/checkout/pull/1777\"\u003eactions/checkout#1777\u003c/a\u003e,\n\u003ca\nhref\u003d\"https://redirect.github.com/actions/checkout/pull/1872\"\u003eactions/checkout#1872\u003c/a\u003e\u003c/li\u003e\n\u003c/ul\u003e\n\u003ch2\u003ev4.1.7\u003c/h2\u003e\n\u003cul\u003e\n\u003cli\u003eBump the minor-npm-dependencies group across 1 directory with 4\nupdates by \u003ca\nhref\u003d\"https://github.com/dependabot\"\u003e\u003ccode\u003e@​dependabot\u003c/code\u003e\u003c/a\u003e in \u003ca\nhref\u003d\"https://redirect.github.com/actions/checkout/pull/1739\"\u003eactions/checkout#1739\u003c/a\u003e\u003c/li\u003e\n\u003cli\u003eBump actions/checkout from 3 to 4 by \u003ca\nhref\u003d\"https://github.com/dependabot\"\u003e\u003ccode\u003e@​dependabot\u003c/code\u003e\u003c/a\u003e in \u003ca\nhref\u003d\"https://redirect.github.com/actions/checkout/pull/1697\"\u003eactions/checkout#1697\u003c/a\u003e\u003c/li\u003e\n\u003cli\u003eCheck out other refs/* by commit by \u003ca\nhref\u003d\"https://github.com/orhantoy\"\u003e\u003ccode\u003e@​orhantoy\u003c/code\u003e\u003c/a\u003e in \u003ca\nhref\u003d\"https://redirect.github.com/actions/checkout/pull/1774\"\u003eactions/checkout#1774\u003c/a\u003e\u003c/li\u003e\n\u003c/ul\u003e\n\u003c!-- raw HTML omitted --\u003e\n\u003c/blockquote\u003e\n\u003cp\u003e... (truncated)\u003c/p\u003e\n\u003c/details\u003e\n\u003cdetails\u003e\n\u003csummary\u003eCommits\u003c/summary\u003e\n\u003cul\u003e\n\u003cli\u003e\u003ca\nhref\u003d\"https://github.com/actions/checkout/commit/df4cb1c069e1874edd31b4311f1884172cec0e10\"\u003e\u003ccode\u003edf4cb1c\u003c/code\u003e\u003c/a\u003e\nUpdate changelog for v6.0.3 (\u003ca\nhref\u003d\"https://redirect.github.com/actions/checkout/issues/2446\"\u003e#2446\u003c/a\u003e)\u003c/li\u003e\n\u003cli\u003e\u003ca\nhref\u003d\"https://github.com/actions/checkout/commit/1cce3390c2bfda521930d01229c073c7ff920824\"\u003e\u003ccode\u003e1cce339\u003c/code\u003e\u003c/a\u003e\nFix checkout init for SHA-256 repositories (\u003ca\nhref\u003d\"https://redirect.github.com/actions/checkout/issues/2439\"\u003e#2439\u003c/a\u003e)\u003c/li\u003e\n\u003cli\u003e\u003ca\nhref\u003d\"https://github.com/actions/checkout/commit/900f2210b1d28bbbd0bd22d17926b9e224e8f231\"\u003e\u003ccode\u003e900f221\u003c/code\u003e\u003c/a\u003e\nfix: expand merge commit SHA regex and add SHA-256 test cases (\u003ca\nhref\u003d\"https://redirect.github.com/actions/checkout/issues/2414\"\u003e#2414\u003c/a\u003e)\u003c/li\u003e\n\u003cli\u003e\u003ca\nhref\u003d\"https://github.com/actions/checkout/commit/0c366fd6a839edf440554fa01a7085ccba70ac98\"\u003e\u003ccode\u003e0c366fd\u003c/code\u003e\u003c/a\u003e\nUpdate changelog (\u003ca\nhref\u003d\"https://redirect.github.com/actions/checkout/issues/2357\"\u003e#2357\u003c/a\u003e)\u003c/li\u003e\n\u003cli\u003eSee full diff in \u003ca\nhref\u003d\"https://github.com/actions/checkout/compare/de0fac2e4500dabe0009e67214ff5f5447ce83dd...df4cb1c069e1874edd31b4311f1884172cec0e10\"\u003ecompare\nview\u003c/a\u003e\u003c/li\u003e\n\u003c/ul\u003e\n\u003c/details\u003e\n\u003cbr /\u003e\n\n\n[![Dependabot compatibility\nscore](https://dependabot-badges.githubapp.com/badges/compatibility_score?dependency-name\u003dactions/checkout\u0026package-manager\u003dgithub_actions\u0026previous-version\u003d6.0.2\u0026new-version\u003d6.0.3)](https://docs.github.com/en/github/managing-security-vulnerabilities/about-dependabot-security-updates#about-compatibility-scores)\n\nDependabot will resolve any conflicts with this PR as long as you don\u0027t\nalter it yourself. You can also trigger a rebase manually by commenting\n`@dependabot rebase`.\n\n[//]: # (dependabot-automerge-start)\n[//]: # (dependabot-automerge-end)\n\n---\n\n\u003cdetails\u003e\n\u003csummary\u003eDependabot commands and options\u003c/summary\u003e\n\u003cbr /\u003e\n\nYou can trigger Dependabot actions by commenting on this PR:\n- `@dependabot rebase` will rebase this PR\n- `@dependabot recreate` will recreate this PR, overwriting any edits\nthat have been made to it\n- `@dependabot show \u003cdependency name\u003e ignore conditions` will show all\nof the ignore conditions of the specified dependency\n- `@dependabot ignore \u003cdependency name\u003e major version` will close this\ngroup update PR and stop Dependabot creating any more for the specific\ndependency\u0027s major version (unless you unignore this specific\ndependency\u0027s major version or upgrade to it yourself)\n- `@dependabot ignore \u003cdependency name\u003e minor version` will close this\ngroup update PR and stop Dependabot creating any more for the specific\ndependency\u0027s minor version (unless you unignore this specific\ndependency\u0027s minor version or upgrade to it yourself)\n- `@dependabot ignore \u003cdependency name\u003e` will close this group update PR\nand stop Dependabot creating any more for the specific dependency\n(unless you unignore this specific dependency or upgrade to it yourself)\n- `@dependabot unignore \u003cdependency name\u003e` will remove all of the ignore\nconditions of the specified dependency\n- `@dependabot unignore \u003cdependency name\u003e \u003cignore condition\u003e` will\nremove the ignore condition of the specified dependency and ignore\nconditions\n\n\n\u003c/details\u003e\n\nSigned-off-by: dependabot[bot] \u003csupport@github.com\u003e\nCo-authored-by: dependabot[bot] \u003c49699333+dependabot[bot]@users.noreply.github.com\u003e" }, { "commit": "37b8c2c1a1a33ca186217a49adbec09035d2772d", "tree": "a99ac6f23ca0a98514c612f82b13e7153d94e64f", "parents": [ "c0348f83c5f835e23903e335dc9090c8950181ae" ], "author": { "name": "Artem Gindinson", "email": "gindinson@roofline.ai", "time": "Wed Jun 03 16:51:25 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Jun 03 14:51:25 2026 +0000" }, "message": "[GlobalOpt][NFC] Update option description for matmul generalization (#24565)\n\nUpdates the inaccurate description." }, { "commit": "c0348f83c5f835e23903e335dc9090c8950181ae", "tree": "985ba5c9462341963db37cea68b3c6624c0220c7", "parents": [ "01baf0ef7e158e8a3ab94bf009187d89626f3c28" ], "author": { "name": "Ege Beysel", "email": "beyselege@gmail.com", "time": "Wed Jun 03 15:23:33 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Jun 03 13:23:33 2026 +0000" }, "message": "[Codegen] Add test for `map_store` transformation of scalable pack ops (#24564)\n\nWith https://github.com/llvm/llvm-project/pull/200216 and the latest\nintegration, the combine layout transformation patterns can handle\nlowering `linalg.pack` operations to `iree_linalg_ext.map_store`s. This\nPR just adds the test.\n\nSigned-off-by: Ege Beysel \u003cbeyselege@gmail.com\u003e" }, { "commit": "01baf0ef7e158e8a3ab94bf009187d89626f3c28", "tree": "ab7f575e6b3c01a2d6db756be7d5488b6ce2b2e1", "parents": [ "8e158ad160a796c5a7c9f6284d002a10a1f97094" ], "author": { "name": "Tobias Fuchs", "email": "9053039+devtbi@users.noreply.github.com", "time": "Wed Jun 03 14:49:51 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Jun 03 14:49:51 2026 +0200" }, "message": "[Runtime] Revive thread-safety analysis (#24560)\n\n(Re-) Enables C++ users of the IREE runtime to use clang\u0027s\nthread-safety-analysis to detect bugs before they materialize.\n\nEnabling thread-safety-analysis attributes behind a\n`defined(__cplusplus) \u0026\u0026 defined(__clang__)` guard.\n\nPrevious attribute placement was non-standard: per\nhttps://gcc.gnu.org/onlinedocs/gcc/Attribute-Syntax.html\n\"An attribute specifier list may appear as part of a struct, union or\nenum specifier. It may go either immediately after the struct, union or\nenum keyword, or after the closing brace\".\n\nSigned-off-by: Tobias Fuchs \u003cfuchs@roofline.ai\u003e" }, { "commit": "8e158ad160a796c5a7c9f6284d002a10a1f97094", "tree": "983a231df3da49a273eb3e5e66f8729aa61f2f25", "parents": [ "5eb55e74f326427ea56b4a2160aa08ff33a9e740" ], "author": { "name": "maxbartel", "email": "bartel@roofline.ai", "time": "Wed Jun 03 13:34:07 2026 +0100" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Jun 03 14:34:07 2026 +0200" }, "message": "[Bazel] Add rt python bindings to bazel (#24553)\n\nThis is the first PR of a longer arc where I will add support to bazel\nfor building the python wheels natively.\n\nDepends on https://github.com/llvm/llvm-project/pull/200516" } ], "next": "5eb55e74f326427ea56b4a2160aa08ff33a9e740" }