[Codegen][CPU] Lower RISC-V V f16 vfmacc, vfwmacc, and Zvfhmin inner_tiled MMA. (#25000)

Lowers the RISC-V V f16 `inner_tiled` MMA paths. Native f16 enums are
already on main from #24858. This adds lowering, the widening
`vfwmacc.vf` pair, and the `+zvfhmin`-only fallbacks. All of them reuse
`lowerRiscvVFmaccLike` and the hoisted accumulator legalization from
#24933. Tile N is `vlen/8`.

| Encoding | `+zvfh` | `+zvfhmin` only |
| --- | --- | --- |
| f16×f16→f16 | `llvm.riscv.vfmacc` (`MMA_RISCV_V_VFMACC_*_F16_F16`) |
`extf` the accumulator to f32, f32 `vfmacc`, `truncf` back
(`*_F16_F16_WIDENF32`) |
| f16×f16→f32 | `llvm.riscv.vfwmacc` (`MMA_RISCV_V_VFWMACC_*_F32_F16`) |
`extf` both panels, then f32 `vfmacc` (`*_F32_F16_CASTF32`) |

`+zvfh` implies `+zvfhmin`. When both are legal, the earlier enum wins:
native `vfmacc` for an f16 accumulator, `vfwmacc` for an f32
accumulator. At VLEN=256 the cost model picks `intrinsics_m` 14
(native), 7 (`vfwmacc`), and 6 (both `+zvfhmin` paths). CASTF32 and
WIDENF32 bill the widened f32 vector operand as f32.

Performance is tracked on #24932. On the X60 (VLEN=256), 1-thread
inner_tiled is faster than the mmt4d ukernel for native f16 and
`vfwmacc`. The 4-thread and 8-thread large shapes are still slower.
Native f16 is non-widening `vfmacc`; the f16 ukernel widens with
`vfwmacc`, so that ratio is not the same instruction sequence. `vfwmacc`
is the closer comparison.

Assisted-by: Cursor

Towards #24311

---------

Signed-off-by: Terence <terrencemahlatini@gmail.com>
Co-authored-by: Cursor <cursoragent@cursor.com>