)]}'
{
  "commit": "fe571e4d5efde141ec437cb4699307df67a38b9c",
  "tree": "6d585275ed1944445fb0a93201bc3c4c44a6a9a7",
  "parents": [
    "024c48b23c0e8721d94e544fa78bcfd291afa439"
  ],
  "author": {
    "name": "Benjamin Maxwell",
    "email": "benjamin.maxwell@arm.com",
    "time": "Mon Jun 24 19:05:55 2024 +0100"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Mon Jun 24 11:05:55 2024 -0700"
  },
  "message": "[LLVMCPU][ArmSME] Rework how Arm streaming mode is set on dispatches (#17646)\n\nPreviously, when the `+sme` feature flag was set Armv9 streaming SVE\r\nmode would be enabled for all dispatch regions lowered with the\r\nfollowing experts:\r\n\r\n- `CPUBufferOpsTileAndVectorize`\r\n- `CPUConvTileAndDecomposeExpert`\r\n- `CPUDoubleTilingExpert`\r\n\r\nThis was not ideal as meant streaming mode could be added to dispatch\r\nregions that made no use of scalable vectors, where the (possibly)\r\nlarger streaming vector length provides no benefit, and there may be a\r\ncost due to other overheads.\r\n\r\nThere was also a flag `--iree-experimental-llvmcpu-arm-force-ssve` which\r\ncontrary to its name _did not_ force streaming SVE mode. What this flag\r\ndid do was disable tiling for 2D scalable ArmSME operations, then rely\r\non something else later on setting the streaming mode (but it did not\r\ncontrol it).\r\n\r\nThe patch aims to add clearer and more directed ways to enable streaming\r\nmode.\r\n\r\nFirst, streaming mode is no longer set in any lowering experts (it\u0027s a\r\nfairly low-level concept, that does not need to be configured early in\r\nthe pipeline). Second, the old\r\n`--iree-experimental-llvmcpu-arm-force-ssve` flag is removed.\r\n\r\nNow to control tiling for ArmSME and using streaming mode there are two\r\nnew flags.\r\n\r\n`iree-llvmcpu-disable-arm-sme-tiling`:\r\n\r\nThis disables tiling for ArmSME (i.e. using 2D scalable tile sizes),\r\neven when the `+sme` feature flag is set. This results in operations\r\ninstead being tiled for SVE or Neon (depending on the configuration).\r\n\r\n`iree-llvmcpu-force-arm-streaming`:\r\n\r\nThis enables Arm streaming mode for any dispatch regions that contain\r\nscalable vectors. It ignores dispatches that don\u0027t contain scalable\r\nvectors as enabling streaming mode would provide no benefit.\r\n\r\nci-extra: build_test_all_arm64\r\n\r\n---------\r\n\r\nSigned-off-by: Benjamin Maxwell \u003cbenjamin.maxwell@arm.com\u003e",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "175c1ae680bd98d250fcf9a364f382bb2942460c",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp",
      "new_id": "9ce86e9a553d713e73a75225454b5821fbf3a2bd",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp"
    },
    {
      "type": "modify",
      "old_id": "6a4363ff47afbac3b8b2ba24abd57b1cfddcea16",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/Passes.cpp",
      "new_id": "10bbc3bfbd28b2737019f7878edb667c3a2152f2",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/Passes.cpp"
    },
    {
      "type": "modify",
      "old_id": "4c4c735a4ad9e7daaf06344305932d77f8292400",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/BUILD.bazel",
      "new_id": "cd9c4e923ec55aac4a327ba28823e99e0ad1125b",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/BUILD.bazel"
    },
    {
      "type": "modify",
      "old_id": "4c66fb49acb628803d4a147c84073caeb22a35ae",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/CMakeLists.txt",
      "new_id": "de22f621fd83fa4807e93d0888d498813d4499cc",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/CMakeLists.txt"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "3ff496a235f41e6d9c2f85aa0a76291735934559",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/pipeline_arm_sme_streaming_mode_tests.mlir"
    },
    {
      "type": "delete",
      "old_id": "f0dae66c99e5b6e86e8c8a64ef121bc1069b2719",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/pipeline_ssve_tests.mlir",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "modify",
      "old_id": "64dc73ded2ae6f083abf09bb41b0da1c666ac94f",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/select_aarch64_sve_lowering_strategy.mlir",
      "new_id": "4944337da30c10f3e4fc1738365c0802284447cd",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/select_aarch64_sve_lowering_strategy.mlir"
    }
  ]
}