)]}'
{
  "commit": "fce95cd99184bb458d191edc2c0d1de7aa9940f7",
  "tree": "e6b5c7cc1e448b253dbc2ba0b6f3176f28647291",
  "parents": [
    "18fe0926981becffb1332ed727aaf916a9727b13"
  ],
  "author": {
    "name": "Abhishek Varma",
    "email": "abhvarma@amd.com",
    "time": "Fri Jan 30 16:34:00 2026 +0530"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Fri Jan 30 11:04:00 2026 +0000"
  },
  "message": "[LLVMCPU] Allow generic conv ops too in KernelDispatch (#23295)\n\n-- Named convolution ops are assigned `CPUConvTileAndDecomposeExpert`\n   and we\u0027d need the same to be in the case of generic convolution\n   ops as well. Changes in this patch achieves are required to enable\n   that.\n-- This is needed to enable generalizing convolution ops as part of\n   https://github.com/iree-org/iree/issues/21955\n\nSigned-off-by: Abhishek Varma \u003cabhvarma@amd.com\u003e",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "f6da74fccf052cbdcc52aeda4f9ceee4b6033166",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp",
      "new_id": "e6d76d54096124792a6c7a69af4f263ecffb5ab3",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp"
    },
    {
      "type": "modify",
      "old_id": "88decba924e8f8b87431c829fc5f435e3c0d7bf6",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/select_aarch64_lowering_strategy.mlir",
      "new_id": "e2729c1de435c42707d8b4cce11569d9f9ca55fd",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/select_aarch64_lowering_strategy.mlir"
    },
    {
      "type": "modify",
      "old_id": "aae25bd088732329d504a1674cbe2aeab8cb153e",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/select_riscv_lowering_strategy.mlir",
      "new_id": "1890935494941541bd2210a27024b6d2e54a2047",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/select_riscv_lowering_strategy.mlir"
    },
    {
      "type": "modify",
      "old_id": "c3a87d6d514daf85fd51a9cb8808fcc396ce7503",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/select_x86_64_lowering_strategy.mlir",
      "new_id": "81f1e2c68621d3db82aa58cbd71766052fc8c6e5",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/select_x86_64_lowering_strategy.mlir"
    }
  ]
}
