[HAL/AMDGPU] Centralize physical topology edge selection Move the physical source/destination topology edge decision table into physical_device_capabilities.*, separating HSA fact collection from policy selection. logical_device.c now queries memory-pool access and link-hop records, then feeds a pure selector that records coarse/fine access, grant-required peer access, PCIe/xGMI/etc link flags, coherency, 32-bit and 64-bit atomics, link class/cost/NUMA distance, and derived HAL topology modes/capabilities. This keeps the queue, command-buffer, and copy hot paths free of new buffer-snooping or recurring validation while giving future SDMA/P2P strategy selection named cold-path facts to consume. Unsupported copy strategies remain feature slots rather than implicit queue-path branches. Add synthetic coverage for xGMI, PCIe without coherent/system-atomic support, multi-hop worst-case collapse, grant-required peer memory, no-access host-staged fallback, and invalid HSA fact inputs.
IREE (Intermediate Representation Execution Eenvironment, pronounced as “eerie”) is an MLIR-based end-to-end compiler and runtime that lowers Machine Learning (ML) models to a unified IR that scales up to meet the needs of the datacenter and down to satisfy the constraints and special considerations of mobile and edge deployments.
See our website for project details, user guides, and instructions on building from source.
Releases notes are published on GitHub releases.
| Package | Release status |
|---|---|
| GitHub release (stable) | |
| GitHub release (nightly) | |
iree-base-compiler | |
iree-base-runtime |
For more details on the release process, see https://iree.dev/developers/general/release-management/.
| Operating system | Build status |
|---|---|
| Linux | |
| macOS | |
| macOS |
For the full list of workflows see https://iree.dev/developers/general/github-actions/.
See our website for more information.
Community meeting recordings: IREE YouTube channel
| Date | Title | Recording | Slides |
|---|---|---|---|
| 2025-06-10 | Data-Tiling in IREE: Achieving High Performance Through Compiler Design (AsiaLLVM) | recording | slides |
| 2025-05-17 | Introduction to GPU architecture and IREE's GPU CodeGen Pipeline | recording | slides |
| 2025-02-12 | The Long Tail of AI: SPIR-V in IREE and MLIR (Vulkanised) | recording | slides |
| 2024-10-01 | Unveiling the Inner Workings of IREE: An MLIR-Based Compiler for Diverse Hardware | recording | |
| 2021-06-09 | IREE Runtime Design Tech Talk | recording | slides |
| 2020-08-20 | IREE CodeGen (MLIR Open Design Meeting) | recording | slides |
| 2020-03-18 | Interactive HAL IR Walkthrough | recording | |
| 2020-01-31 | End-to-end MLIR Workflow in IREE (MLIR Open Design Meeting) | recording | slides |
IREE is licensed under the terms of the Apache 2.0 License with LLVM Exceptions. See LICENSE for more information.