)]}'
{
  "commit": "f4d1908e89fece7e0bf5cebd606b69a9483817f3",
  "tree": "872e5fcb34d591273dcf19ccd3d6e2b24723b42e",
  "parents": [
    "7098bdfec0fa62ce250e9a99b0977dbb86b4fcf0"
  ],
  "author": {
    "name": "Zhewen Yu",
    "email": "zhewenyu@amd.com",
    "time": "Fri May 01 22:48:38 2026 +0100"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Fri May 01 22:48:38 2026 +0100"
  },
  "message": "[Codegen][DMA] Fix unaligned swizzle offset computation in gather-to-lds lowering (#24241)\n\nThe inverse XOR swizzle applied to DMA source offsets was incorrect in\ntwo cases:\n\n1. **Subgroup base offset**: When a subgroup\u0027s transfer size is not a\nmultiple of the swizzle period, different subgroups sharing the same\nlocal offsets but occupying different rows would get identical swizzled\naddresses.\n\nFix: incorporate the subgroup\u0027s base offset within the full allocation\nbefore swizzling.\n\n2. **Access-width alignment**: When `elementsPerLane \u003c accessWidth`, the\ninteger division inside `swizzleOffset` truncates offsets that differ\nonly within an access-width group to the same value.\n\nFix: strip the sub-accesswidth remainder before swizzling and restore it\nafter. This fix is applied directly in `swizzleOffset` for both XOR and\nrotate_rows swizzles. While rotate_rows isn\u0027t currently used with DMA,\nthe access-width alignment issue affects both swizzle types.\n\nBoth issues caused numerical mismatches for BF16 batch matmuls using DMA\nwith XOR swizzle enabled.\n\nAssisted-by: Cursor (Claude)\n\n---------\n\nSigned-off-by: Yu-Zhewen \u003czhewenyu@amd.com\u003e",
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