)]}'
{
  "commit": "efb87ccf277e8725c06967e1442cc3504a22fc58",
  "tree": "634c6c66a234c2ffc5da2b03047f94c06f1fc297",
  "parents": [
    "5abc965413a1e40d03c91764f053db92767aeccb"
  ],
  "author": {
    "name": "Ege Beysel",
    "email": "beysel@roofline.ai",
    "time": "Fri Aug 21 17:09:03 2026 +0200"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Fri Aug 21 17:09:03 2026 +0200"
  },
  "message": "[LLVMCPU] set inner-tile alignment hints on scalable unpack ops (#24808)\n\nExtend setting the inner tile alignment hints to `linalg.unpack` ops.\nAfter the loop tile sizes are in the unpacked domain, the inner tile\nsizes are compared with these to infer aligment hints per-tiling level\nand the corresponding attribute is set.\n\nAssisted-by: Claude Code\n\n---\n\n\u003csub\u003eStack created with \u003ca\nhref\u003d\"https://github.com/github/gh-stack\"\u003eGitHub Stacks CLI\u003c/a\u003e • \u003ca\nhref\u003d\"https://gh.io/stacks-feedback\"\u003eGive Feedback 💬\u003c/a\u003e\u003c/sub\u003e\n\nSigned-off-by: Ege Beysel \u003cbeyselege@gmail.com\u003e",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "bc93f7bed44245ef2c839377591592ba56863a32",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp",
      "new_id": "a195a53dd87c5c68ddd77ac1fd5bdf1ddd92ad45",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp"
    },
    {
      "type": "modify",
      "old_id": "f7b1628f96ef99029146680ec1e066fd63ea8ef3",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/select_aarch64_sve_lowering_strategy.mlir",
      "new_id": "eae3c8889fd7784bc868ac7e4de8a0467f478b7a",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/select_aarch64_sve_lowering_strategy.mlir"
    },
    {
      "type": "modify",
      "old_id": "5fbb57d3ae7b22ee723194558bd815ed6c0bc121",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/select_riscv_v_lowering_strategy.mlir",
      "new_id": "b772d811655e70e977c368e10996faff3eccec24",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/select_riscv_v_lowering_strategy.mlir"
    }
  ]
}
