)]}' { "commit": "ed65de2d362643826127cc750b9ae7ac562bf877", "tree": "5bc32c07c9d13f04d199b5056fa58c152ffcaaa1", "parents": [ "8f79b944b164b956bf29b85a18ab50ee2292e0cd" ], "author": { "name": "Pooja Hemashekar", "email": "hemashekar@roofline.ai", "time": "Thu Oct 08 16:03:56 2026 +0200" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Thu Oct 08 16:03:56 2026 +0200" }, "message": "Integrate LLVM to llvm/llvm-project@7e751154a0e5 (#25009)\n\nBumps LLVM to llvm/llvm-project@7e751154a0e5. The GPU min/maxnumf carry\npatch is dropped now that it landed upstream\n(llvm/llvm-project@2e686411fa67).\n\nCompatibility changes:\n\n- Migrate AMDGPU target handling from the deprecated `amdgpu::Chipset`\n(ISA version numbers) to `ROCDL::TargetInfo` (target feature queries),\nfollowing llvm/llvm-project@155462f440ff. The upstream AMDGPU/ROCDL\nlowering entry points now take a `ROCDL::TargetInfo`, and the remaining\n`Chipset` uses in IREE are migrated too since the deprecation warnings\nfail the Bazel `-Werror` build. Behavior is preserved except where\nupstream corrected it:\n- Barriers on targets without hardware barrier back-off (e.g. gfx90c)\nuse the inline-asm `s_barrier` form, matching upstream.\n - OCP fp8 conversions are also recognized on gfx11.7.\n- The wave64 flag for the HIP platform globals is derived from the\ntarget, so wave32-only targets such as gfx1250 are handled correctly.\n- Carry the MMA slice-cache correction for the regression introduced by\nllvm/llvm-project@d287e55d0302.\n\nAssisted-by: Claude Code\n\nSigned-off-by: Pooja Hemashekar \u003chemashekar@roofline.ai\u003e", "tree_diff": [ { "type": "modify", "old_id": "ed8ae58d02e00595bfa66330c2d32c723a30ac06", "old_mode": 33188, "old_path": "compiler/plugins/target/ROCM/BUILD.bazel", "new_id": "ce4981fa20d777365dff136b4dc210c1c02ee48d", "new_mode": 33188, "new_path": "compiler/plugins/target/ROCM/BUILD.bazel" }, { "type": "modify", "old_id": "7a77b04b854f3b7f0f2c21ae8fa03a220c3644c7", "old_mode": 33188, "old_path": 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