)]}'
{
  "commit": "eb694f10eae82dde5f694d674ccf34fdfb562ba4",
  "tree": "4da052d05841eb1880e877a2d539817050ff86c0",
  "parents": [
    "e3936dca933893a8849195989db8b9e5a0893316"
  ],
  "author": {
    "name": "Quinn Dawkins",
    "email": "quinn.dawkins@gmail.com",
    "time": "Fri Aug 23 15:14:29 2024 -0400"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Fri Aug 23 15:14:29 2024 -0400"
  },
  "message": "[Codegen][GPU] Handle dynamic and unaligned cases in DerivedThreadConfig (#18281)\n\nThis adds a default set of tile sizes for any dynamically shaped\r\ncopy/linalg ops that just uses the preferred vector size based on the\r\nelement type bitwidth of the linalg op. This same logic might also be\r\nworth applying in aligned cases, but this patch is opting not to change\r\npre-existing behavior without proper benchmarking.\r\n\r\nAdditionally cleans up the tiling tests.",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "1b9cc625b073d97c205d98c4c56d3eab00ec9829",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/Common/GPU/test/gpu_apply_tiling_level.mlir",
      "new_id": "7c4cd2f047e7f11915728b5659f3f52f4d71ecfa",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/Common/GPU/test/gpu_apply_tiling_level.mlir"
    },
    {
      "type": "modify",
      "old_id": "64af9ddb42c5395c8c2c1f694db9e069896cc217",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/Dialect/GPU/IR/DerivedConfigUtils.cpp",
      "new_id": "72dd92cf90d6ba8a678811261742f04f163fa482",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/Dialect/GPU/IR/DerivedConfigUtils.cpp"
    },
    {
      "type": "modify",
      "old_id": "991450905b73c96b64f1cb712d9aebfe54b9aaef",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/pipeline_tile_and_fuse.mlir",
      "new_id": "a9f320c90603579563b89e5758a566c4a0a919b3",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/pipeline_tile_and_fuse.mlir"
    }
  ]
}