[LLVMGPU] Fix hardcoded LHS transpose shape in NV mma.sync lowering (#24676)

This PR is stacked on:
- [x] https://github.com/iree-org/iree/pull/24659

## Description

`createMmaOp()` hardcoded the LHS reshape shape to `{2, 2, 2}` when
lowering NV `mma.sync`. This held for all NV intrinsics that existed at
the time (F16/BF16 m16n8k16, `element[K]=2`), but FP8 m16n8k32 packs
`element[K]=4`, so the reshape produced 16 elements while the hardcoded
target expected 8:


> error: 'vector.shape_cast' op has different number of elements at
source (16) and result (8)
> note: see current operation: %73 = "vector.shape_cast"(%70) :
(vector<2x1x2x4xf8E4M3FN>) -> vector<2x2x2xf8E4M3FN>

This computes the reshape shape from `getSingleSubgroupLayout()` instead
of hardcoding it, so it adapts to any `element[K]` size. F16/BF16
behavior is unchanged (`{2, 2, 2}` still holds for them).

Adds an FP8 (E4M3FN) TileAndFuse pipeline test.

## Testing

```bash
/workspace/iree-build/tools/iree-opt \
    --split-input-file \
    --iree-codegen-llvmgpu-nvvm-lowering-pipeline="include-llvm-lowering=false" \
    compiler/src/iree/compiler/Codegen/LLVMGPU/test/NVVM/pipeline_tile_and_fuse_mma_sync.mlir \
    | /workspace/iree-build/llvm-project/bin/FileCheck \
      compiler/src/iree/compiler/Codegen/LLVMGPU/test/NVVM/pipeline_tile_and_fuse_mma_sync.mlir

---------

Signed-off-by: weimin023 <tnwilly@gmail.com>