)]}'
{
  "commit": "e7490c3b04a1ca2d771533904a5b6fddb4be4371",
  "tree": "183e675de896f8e288f57be29499993022a2e5a0",
  "parents": [
    "9ea0f2f2ed2c922b1df32a856ed9ca037b086657"
  ],
  "author": {
    "name": "tm",
    "email": "terrencemahlatini@gmail.com",
    "time": "Wed Oct 21 03:48:26 2026 -0500"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Wed Oct 21 08:48:26 2026 +0000"
  },
  "message": "[Codegen][CPU] Lower RISC-V V f16 vfmacc, vfwmacc, and Zvfhmin inner_tiled MMA. (#25000)\n\nLowers the RISC-V V f16 `inner_tiled` MMA paths. Native f16 enums are\nalready on main from #24858. This adds lowering, the widening\n`vfwmacc.vf` pair, and the `+zvfhmin`-only fallbacks. All of them reuse\n`lowerRiscvVFmaccLike` and the hoisted accumulator legalization from\n#24933. Tile N is `vlen/8`.\n\n| Encoding | `+zvfh` | `+zvfhmin` only |\n| --- | --- | --- |\n| f16×f16→f16 | `llvm.riscv.vfmacc` (`MMA_RISCV_V_VFMACC_*_F16_F16`) |\n`extf` the accumulator to f32, f32 `vfmacc`, `truncf` back\n(`*_F16_F16_WIDENF32`) |\n| f16×f16→f32 | `llvm.riscv.vfwmacc` (`MMA_RISCV_V_VFWMACC_*_F32_F16`) |\n`extf` both panels, then f32 `vfmacc` (`*_F32_F16_CASTF32`) |\n\n`+zvfh` implies `+zvfhmin`. When both are legal, the earlier enum wins:\nnative `vfmacc` for an f16 accumulator, `vfwmacc` for an f32\naccumulator. At VLEN\u003d256 the cost model picks `intrinsics_m` 14\n(native), 7 (`vfwmacc`), and 6 (both `+zvfhmin` paths). CASTF32 and\nWIDENF32 bill the widened f32 vector operand as f32.\n\nPerformance is tracked on #24932. On the X60 (VLEN\u003d256), 1-thread\ninner_tiled is faster than the mmt4d ukernel for native f16 and\n`vfwmacc`. The 4-thread and 8-thread large shapes are still slower.\nNative f16 is non-widening `vfmacc`; the f16 ukernel widens with\n`vfwmacc`, so that ratio is not the same instruction sequence. `vfwmacc`\nis the closer comparison.\n\nAssisted-by: Cursor\n\nTowards #24311\n\n---------\n\nSigned-off-by: Terence \u003cterrencemahlatini@gmail.com\u003e\nCo-authored-by: Cursor \u003ccursoragent@cursor.com\u003e",
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