)]}'
{
  "commit": "e3f2ab393fdef5a22877c982f8e2e89effdbfa91",
  "tree": "0e74f3d96d131f3e81654846bfdee844f42fca4b",
  "parents": [
    "41a23ade9c5857ec56a70e3cb907ffaa9feb6c5e"
  ],
  "author": {
    "name": "Han-Chung Wang",
    "email": "hanhan0912@gmail.com",
    "time": "Tue Nov 07 09:45:51 2023 -0800"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Tue Nov 07 09:45:51 2023 -0800"
  },
  "message": "[CPU] Improve tile sizes selection for tensor.pack ops. (#15397)\n\nIt disables special vector sizes for non-f32 cases because the logic is\r\nonly for 16x16 transpose cases. The improvements of dispatch sizes are\r\nfrom vectorization. We are not able to vectorize named ops if they have\r\ndynamic shapes, which is fixed by\r\nhttps://github.com/llvm/llvm-project/commit/03529b99b36788ca836b7ce238ea9400ce89847b.\r\nThe change allows backends to vectorize them because they become static\r\nshapes (by tiling with size\u003d1). It is not a hard condition; we track it\r\nin https://github.com/openxla/iree/issues/15441\r\n\r\nThe revision takes the number of threads into account, so we have better\r\nperformance on multi-threaded. It also reduces runtime overheads.\r\n\r\nThis is a step toward to https://github.com/openxla/iree/issues/15391\r\nand https://github.com/openxla/iree/issues/15349\r\n\r\nIt improves the performance of\r\n[tensor.pack](https://github.com/openxla/iree/issues/15349) op from 420\r\nms to 170 ms on 8-threaded x86 CPU.",
  "tree_diff": [
    {
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      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp",
      "new_id": "b7f8571f2128f92cdadc0645ec0181019ab85c68",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp"
    },
    {
      "type": "modify",
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      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/materialize_aarch64_launch_configuration.mlir",
      "new_id": "2d845427283e2718f94a487814192764f6a24cbc",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/materialize_aarch64_launch_configuration.mlir"
    },
    {
      "type": "modify",
      "old_id": "6c3d4952cd6eb810f01d2fea97e05108628ecc91",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/materialize_x86_64_launch_configuration.mlir",
      "new_id": "834462f0c87b62dbe37d23ba426103fe69c91319",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/materialize_x86_64_launch_configuration.mlir"
    }
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}