diff --git a/compiler/src/iree/compiler/Codegen/Dialect/GPU/IR/IREEGPUAttrs.td b/compiler/src/iree/compiler/Codegen/Dialect/GPU/IR/IREEGPUAttrs.td
index c3514d6..8222117 100644
--- a/compiler/src/iree/compiler/Codegen/Dialect/GPU/IR/IREEGPUAttrs.td
+++ b/compiler/src/iree/compiler/Codegen/Dialect/GPU/IR/IREEGPUAttrs.td
@@ -172,6 +172,7 @@
 
 //===----------------------------------------------------------------------===//
 // MMA intrinsic
+//===----------------------------------------------------------------------===//
 
 class IREEGPU_MmaEnumAttr<EnumAttrInfo enumInfo, string name = "">
   : EnumAttr<IREEGPU_Dialect, enumInfo, name>;
@@ -186,12 +187,8 @@
   let description = !strconcat(baseDescription, [{
     This mma variant describes configurations for MMA ops. The |intrinsic|
     field specifies which particular MMA intrinsic this refers to, with each
-    intrinsic implicating a specific MNK shape and operand types. The intrinsic
-    enum name describes these fields as
-
-    <InputType>_MxNxK_<CType>
-
-    Where the element type for the `A` and `B` matrices are both `InputType`.
+    intrinsic implicating a specific MNK shape and operand types.
+    See IREEGPUEnums.td for the definition of the intrinsics.
   }]);
 
   let hasCustomAssemblyFormat = 1;
@@ -230,6 +227,7 @@
 
 //===----------------------------------------------------------------------===//
 // MMA schedule
+//===----------------------------------------------------------------------===//
 
 def IREEGPU_MmaScheduleAttr : AttrDef<IREEGPU_Dialect, "MMASchedule"> {
   let mnemonic = "mma_schedule";
@@ -259,6 +257,7 @@
 
 //===----------------------------------------------------------------------===//
 // Workgroup processor level description
+//===----------------------------------------------------------------------===//
 
 def IREEGPU_TargetWgpAttr : AttrDef<IREEGPU_Dialect, "TargetWgp"> {
   let summary = "Workgroup processor level target description";