[LinalgExt] Fix WinogradInputTransformOp::verify incorrect dim-1 dynamic check (#24679)
### Problem
`WinogradInputTransformOp::verify` never validates the size of input
dimension 1 for rank-2 inputs.
### Root cause
```cpp
if ((!inputType.isDynamicDim(0) &&
inputType.getDimSize(0) > getInputTileSize()) ||
(inputType.isDynamicDim(1) && // <-- missing `!`
inputType.getDimSize(1) > getInputTileSize())) {
return op->emitOpError("expected input dims not greater than input tile "
"size if input is of rank 2");
}
```
The dim-0 clause guards with `!isDynamicDim(0)`, but the dim-1 clause is
missing the `!`, which makes it dead:
- if dim 1 is **static**, `isDynamicDim(1)` is false, so the clause
short-circuits and the static size is never compared;
- if dim 1 is **dynamic**, `getDimSize(1)` is `ShapedType::kDynamic`
(`INT64_MIN`), and `INT64_MIN > getInputTileSize()` (a small positive
tile size) is always false.
So a rank-2 input whose static dim 1 exceeds the input tile size is
silently accepted, contradicting the op's own diagnostic (`expected
input dims not greater than input tile size if input is of rank 2`).
`verifyCompatibleShape` a few lines below only constrains the output
shape, so nothing else catches it.
### Fix
Add the missing `!`, mirroring the dim-0 clause one line above.
### Testing
Static reasoning only (no local build). I'm happy to add a
`--verify-diagnostics` case to `Dialect/LinalgExt/IR/test/invalid.mlir`,
but there is currently no rank-2 `winograd.input_transform` example
in-tree to mirror, so I left the test out of this minimal one-character
fix — glad to add one if you'd like.
---------
Signed-off-by: Eylon Krause <eylon1909@gmail.com>IREE (Intermediate Representation Execution Environment, pronounced as “eerie”) is an MLIR-based end-to-end compiler and runtime that lowers Machine Learning (ML) models to a unified IR that scales up to meet the needs of the datacenter and down to satisfy the constraints and special considerations of mobile and edge deployments.
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Community meeting recordings: IREE YouTube channel
| Date | Title | Recording | Slides |
|---|---|---|---|
| 2025-06-10 | Data-Tiling in IREE: Achieving High Performance Through Compiler Design (AsiaLLVM) | recording | slides |
| 2025-05-17 | Introduction to GPU architecture and IREE's GPU CodeGen Pipeline | recording | slides |
| 2025-02-12 | The Long Tail of AI: SPIR-V in IREE and MLIR (Vulkanised) | recording | slides |
| 2024-10-01 | Unveiling the Inner Workings of IREE: An MLIR-Based Compiler for Diverse Hardware | recording | |
| 2021-06-09 | IREE Runtime Design Tech Talk | recording | slides |
| 2020-08-20 | IREE CodeGen (MLIR Open Design Meeting) | recording | slides |
| 2020-03-18 | Interactive HAL IR Walkthrough | recording | |
| 2020-01-31 | End-to-end MLIR Workflow in IREE (MLIR Open Design Meeting) | recording | slides |
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