)]}'
{
  "commit": "db677a83d8c0cf5c3aa46c13dcb38298d9b2b1c7",
  "tree": "31204fe310d11ac153ab0e3de00594782d75fa61",
  "parents": [
    "9dc8ae413b4a52495876c5efb86e01186efdc111"
  ],
  "author": {
    "name": "Quinn Dawkins",
    "email": "quinn.dawkins@gmail.com",
    "time": "Tue Feb 27 09:38:13 2024 -0500"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Tue Feb 27 14:38:13 2024 +0000"
  },
  "message": "[Codegen][ROCDL] Add support for nhwc convolution with mfma (#16579)\n\nThis supports convolutions using the matmul pipeline by simply tiling\r\nthe kernel dimensions to 1 and then folding them away, leaving a\r\ncontraction along the remaining image/input channel dimensions. The\r\nconfig selection logic is kept the same as matmul for now, ignoring the\r\nadditional dimensions.\r\n\r\nThis only support nhwc convolutions, however supporting nchw\r\nconvolutions is simply a matter of supporting matmul_transpose_a\r\nvariants. This also does not support strided convolutions because this\r\napproach will fail to vectorize in such cases.",
  "tree_diff": [
    {
      "type": "modify",
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      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMGPU/KernelConfig.cpp",
      "new_id": "48fa7975439f7852ac2bafd4167f181c94b9aa9e",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMGPU/KernelConfig.cpp"
    },
    {
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      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMGPU/Passes.cpp",
      "new_id": "7920f219fd7f8045113a9660496ce7ad0e31de92",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMGPU/Passes.cpp"
    },
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      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/config_vector_distribute.mlir",
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      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/config_vector_distribute.mlir"
    },
    {
      "type": "modify",
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      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/pipeline_vector_distribute.mlir",
      "new_id": "31bdc4439dec51069c4d33afb230fe3f9803cd3d",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/pipeline_vector_distribute.mlir"
    }
  ]
}