)]}'
{
  "commit": "db590705390f7182d8d329483585265ab5524dcf",
  "tree": "ec822aa6c9f88a99a0f3175931312df294ee37d7",
  "parents": [
    "bb542eee65fa0a498963df1f2ee2f205a3dd8bd0"
  ],
  "author": {
    "name": "Nirvedh Meshram",
    "email": "96096277+nirvedhmeshram@users.noreply.github.com",
    "time": "Fri Nov 01 11:26:56 2024 -0500"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Fri Nov 01 11:26:56 2024 -0500"
  },
  "message": "[GPU] Disable unaligned to instrinsic batch matmul codegen with vector distribute (#18935)\n\nThis path doesnt support all batch matmul shapes but tries to and fails \r\ne.g. https://github.com/iree-org/iree/issues/18601\r\n\r\nSo this PR makes this change because by default we should favor higher\r\nfunctionality support over performance. Solution is to keep this path\r\nbehind a flag which is off by default.\r\n\r\nFixes : https://github.com/iree-org/iree/issues/18601\r\n\r\nIf we bail out here, we will go down SIMT (note that we do anyway for\r\nnon batch matmul GEMMs for such shapes) for now with Tile and Fuse\r\npipeline support planned for the future. In the time being models who\r\nhave shapes that are supported by this path can do so using the provided\r\nflag. And tuners can always use this pipeline if it works for the shape.\r\nWe can also turn this on by default if we can add correct heuristics on\r\nwhen it is okay to use this path.\r\n\r\n---------\r\n\r\nSigned-off-by: Nirvedh \u003cnirvedh@gmail.com\u003e",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "b4567e32938d0cbee93d7e0f57d475dfc77a5491",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMGPU/KernelConfig.cpp",
      "new_id": "344565bd9992c4d5100335236caaf316fb92f890",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMGPU/KernelConfig.cpp"
    },
    {
      "type": "modify",
      "old_id": "a15177de28b0af4107ba00cd50de4d578bf2b980",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/config_vector_distribute_gfx940.mlir",
      "new_id": "da6a563c676d0c2e967ea44ee2b471b1d279e623",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/config_vector_distribute_gfx940.mlir"
    }
  ]
}