)]}'
{
  "commit": "cff4b04858d8207a5c94f113bbf99407a1322db7",
  "tree": "0def8c97e1091f1389d83e77f6d3fac7fc30ae1f",
  "parents": [
    "7af48c8886eb3d733e9a54156adbe82292a5841b"
  ],
  "author": {
    "name": "Benoit Jacob",
    "email": "jacob.benoit.1@gmail.com",
    "time": "Fri May 15 15:38:45 2026 -0400"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Fri May 15 15:38:45 2026 -0400"
  },
  "message": "[Codegen][CPU] Add e2e matmul tests for the inner_tiled lowering path. (#24492)\n\nAdds an `e2e_matmul_cpu_dt_inner_tiled_*` family that mirrors the\nexisting legacy-path `e2e_matmul_cpu_dt_*` block (same type matrix:\ni8/i32, f32/f32, f64/f64, f16/f16, f16/f32, bf16/bf16, bf16/f32; same\nper-type x86 cpu-features variants; f64-demote guard; riscv/wasm tags)\nbut with `--iree-opt-data-tiling --iree-llvmcpu-enable-inner-tiled`.\n\nType×feature combos that match a hardware MMA intrinsic (e.g. f32/f32 on\nAVX2, bf16/f32 on AVX-512-BF16, i8/i32 on AVX-512-VNNI) exercise the new\n`iree_codegen.inner_tiled` lowering; the rest fall through to the\ntype-polymorphic generic-scalar MMA (#24389), so this is a correctness\ncheck on data-tiling-enabled compilation either way.\n\nShapes use the `default` set, except f64 (`small`, due to f64-demote\nhandling). The prerequisite pre-transposed-enum PR is what lets us start\nat the full shape set rather than progressively widen.\n\nProgress towards #24323.\n\n---------\n\nSigned-off-by: Benoit Jacob \u003cjacob.benoit.1@gmail.com\u003e",
  "tree_diff": [
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