[HAL/AMDGPU] Model target feature support

Extend the generated AMDGPU target map so exact target rows also carry XNACK/SRAMECC feature-support bits. The target-ID parser now uses that shared table to normalize known unsupported features to UNSUPPORTED while preserving supported but unspecified modes as ANY, which keeps the ROCr wildcard-vs-explicit compatibility distinction intact without adding another hand-written target database.

Record the physical-device HSA ISA identity as one nested isa field instead of a loose processor buffer plus duplicated gfx IP version. Queue/profile policy now consumes isa.target_id.version, and system info caches HSA_AMD_SYSTEM_INFO_XNACK_ENABLED as the process-wide KFD-bound XNACK mode. That gives later topology and executable-load code a named cold-path place to ask about agent identity instead of rediscovering feature state.

Tighten multi-GPU ISA commonality diagnostics by comparing parsed target IDs and reporting processor, generic-version, SRAMECC, and XNACK mismatches by name. Mixed feature modes were previously only visible as raw string differences, which was technically useful but not the invariant we need for day-0 CDNA/RDNA support.