)]}'
{
  "commit": "cbfefdbf92f655d04f49b8343fef90306d05dd4d",
  "tree": "b1c9c7513c76d6a0923234f697e56cf1af14382f",
  "parents": [
    "9983d03e4f1a097414addd99cae964fb542d4ba5"
  ],
  "author": {
    "name": "Ege Beysel",
    "email": "beysel@roofline.ai",
    "time": "Wed Aug 19 07:05:08 2026 +0200"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Wed Aug 19 07:05:08 2026 +0200"
  },
  "message": "[LLVMCPU] set inner-tile alignment hints on scalable pack ops (#24807)\n\nDuring tile size selection, global tile sizes and mappings to each\noperation are available. Here, each scalable `linalg.pack` inner tile is\ncompared against the loop tile size chosen for that dimension and\ncorresponding inner tile alignment hints are set. This is done before\nthe loop tile sizes for the pack op are translated into the packed outer\ndomain.\n\nOn the other hand, a `linalg.pack` whose producer is a `linalg.unpack`\nis pruned by MultiLoweringConfigGenerator and never receives a lowering\nconfig, so it is handled separately by reading the producer unpack\u0027s\nper-level tile sizes and comparing them against the pack\u0027s scalable\ninner tiles.\n\nAssisted-by: Claude Code\n\n---\n\n\u003csub\u003eStack created with \u003ca\nhref\u003d\"https://github.com/github/gh-stack\"\u003eGitHub Stacks CLI\u003c/a\u003e • \u003ca\nhref\u003d\"https://gh.io/stacks-feedback\"\u003eGive Feedback 💬\u003c/a\u003e\u003c/sub\u003e\n\n---------\n\nSigned-off-by: Ege Beysel \u003cbeyselege@gmail.com\u003e",
  "tree_diff": [
    {
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      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp",
      "new_id": "bc93f7bed44245ef2c839377591592ba56863a32",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp"
    },
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      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/select_aarch64_sve_lowering_strategy.mlir"
    },
    {
      "type": "modify",
      "old_id": "f63738f2f763867e0437ccbf49fee288e555495e",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/select_riscv_v_lowering_strategy.mlir",
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      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/select_riscv_v_lowering_strategy.mlir"
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}