)]}'
{
  "commit": "cbea6b2670f56ba20134408b222d41c911f36cf8",
  "tree": "68873d9ef38c0cbeda25c8257cb3a22ea5ae2fd0",
  "parents": [
    "450f0c80a0a27ca90c158ce280b98c9991e80b52"
  ],
  "author": {
    "name": "Han-Chung Wang",
    "email": "hanchung@google.com",
    "time": "Thu Mar 24 23:24:37 2022 -0700"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Thu Mar 24 23:24:37 2022 -0700"
  },
  "message": "[NFC] Add StrategyTilingLevel enum class to clear tiling level meaning. (#8633)\n\nThe codegen used to use TilingLevel::L1Tiles and\r\nTilingLevel::VectorTiles. This is confusing in strategy approach because\r\nthey are not targeting tiling sizes for L1 and vector. They are actually\r\nthe tiling sizes for parallel dims and reduction dims. Correct the\r\nvariable name to make confusion less.",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "138d7cdda977b740723a59e0b465182c7aefd089",
      "old_mode": 33188,
      "old_path": "iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp",
      "new_id": "eb0ea6beb0248b0b8aef03dbf75e90435819a902",
      "new_mode": 33188,
      "new_path": "iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp"
    },
    {
      "type": "modify",
      "old_id": "afb616e8cb08ce3d39dcf0d4483a3a65ec868543",
      "old_mode": 33188,
      "old_path": "iree/compiler/Codegen/LLVMCPU/KernelDispatch.h",
      "new_id": "f462682aa6f1cfd934cf4c376582834b1b557800",
      "new_mode": 33188,
      "new_path": "iree/compiler/Codegen/LLVMCPU/KernelDispatch.h"
    },
    {
      "type": "modify",
      "old_id": "b039615ce52c89c0caa4943ff6180881bc7eab9c",
      "old_mode": 33188,
      "old_path": "iree/compiler/Codegen/LLVMCPU/Passes.cpp",
      "new_id": "d6c2e1eb873950f9c4fcdfae4be60dbafe7bb5cc",
      "new_mode": 33188,
      "new_path": "iree/compiler/Codegen/LLVMCPU/Passes.cpp"
    },
    {
      "type": "modify",
      "old_id": "a8ac4f8f8df0a0deb18f0c52b26bb2ab1027a6c1",
      "old_mode": 33188,
      "old_path": "iree/compiler/Codegen/LLVMCPU/test/illegal_configuration.mlir",
      "new_id": "0acba0e327ed6f37dad578c86c39d30e004c2379",
      "new_mode": 33188,
      "new_path": "iree/compiler/Codegen/LLVMCPU/test/illegal_configuration.mlir"
    }
  ]
}
