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{
  "commit": "ca7e06373768634a9a4a857ce7dd543f299886b2",
  "tree": "e10d26579041fdc9b76baf162e78e7c5e8ad222f",
  "parents": [
    "c6525dd763ae1414b3715b6beb56957e2383a41c"
  ],
  "author": {
    "name": "Lukas Sommer",
    "email": "lukas.sommer@amd.com",
    "time": "Wed May 06 17:18:51 2026 +0200"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Wed May 06 17:18:51 2026 +0200"
  },
  "message": "[VectorDistribute] Lower and distribute `async_dma` (#24299)\n\nPass to distribute and lower `async_dma` operations at the workgroup\nlevel to `amdgpu.gather_to_lds` operations at the thread-level (with\nthreads in each subgroup collaborating).\n\nThe pass shares helpers with the existing GPU pass to distribute\noperations based on layouts, but as the `async_dma` operation does not\nhave `vector` operands or results, lowering and distribution are\nimplemented as a separate pass. The changes to\n`GPUNestedLayoutDistributionPatterns.cpp` are therefore mainly a code\nmove extracting shared helpers to the new\n`GPUNestedLayoutUtils.[h|cpp]`.\n\nThe basic idea of the distribution is to construct a (nested) layout\nthat represents how the data-transfer is split across subgroups and\nthreads to perform the full transfer with direct-to-LDS compatible\noperations. The layout is constructed in stages:\n1. We choose the DMA size for the given target that fulfills the\nrequirements and determine the element tile based on the size of the\ntransfer per thread from the DMA size (`distributeFromInnermost`).\n2. The element tile is given by the number of threads in subgroup\n(`distributeFromInnermost`).\n3. Outer tile is always all-ones.\n4. We distribute the transfer to the configured number of subgroups\n(`distributeFromOutermost`).\n5. Whatever is left after these steps ends up as the batch tile of each\nthread.\n\nOnce we have that layout, we can use the shared helpers for the\nmechanics of distributing the operation.\n\nThe distribution fails if any of the requirements are not met. This is\nmostly a defensive check, the pass inserting the `async_dma` operations\n(will be added in a different PR) should only insert `async_dma`\noperations if the prerequisites can be met with the available DMA sizes\nfor the transfer shape etc. Therefore, the pass also fails if any of the\n`async_dma` operations could not be distributed and lowered.\n\nSwizzling and gather semantics are not part of this PR and will be added\nin follow-up PRs.\n\nThis is part of https://github.com/iree-org/iree/issues/23782.\n\nAssisted-by: Claude Code and Codex\n\n---------\n\nSigned-off-by: Lukas Sommer \u003clukas.sommer@amd.com\u003e",
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