)]}'
{
  "commit": "c85a426ab7035e0c86d4493e461a1bfbaf5c9b0c",
  "tree": "01799ff87c75e55306faf694671c65f72619c7ef",
  "parents": [
    "89397936163176c035d4f8eb6c8d33b7ceb9f360"
  ],
  "author": {
    "name": "MaheshRavishankar",
    "email": "1663364+MaheshRavishankar@users.noreply.github.com",
    "time": "Thu Feb 04 17:31:42 2021 -0800"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Thu Feb 04 17:31:42 2021 -0800"
  },
  "message": "Enable lowering of Linalg on tensors on GPU. (#4688)\n\no enable the linalg on tensors path on GPU several changes are needed\r\n\r\nThe Bufferization pass is modified to not require allocation in\r\nsome trivial cases. This gets the basic plumbing verified, but\r\nthere are issues with handling allocations that are dynamic on the\r\nSPIR-V side. A more general solution is required here.\r\nThe use of View instructions is dropped since ViewOp cannot be\r\nlowered to SPIR-V.\r\nAll bufferization related passes are moved into\r\niree/compiler/Conversion/Common to use on both SPIR-V and LLVM side.\r\nConvertToSPIRV pass updated to handle the new hal.interface operations\r\nthat are used on the linalg on tensors path.\r\nThe LinalgTileAndFusePass is updated to operate on\r\nIREE::HAL::ExecutableTargetOp. This allows this pass to initialize\r\nthe region that computes number of workgroups in the\r\nIREE::HAL::EntryPointOp. This also requires the pipeline that lowers\r\nto SPIR-V to use the IREE::HAL::ExecutableTargetOp directly.",
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