)]}'
{
  "commit": "c6753332aa7781e7813b87118173a04911366b76",
  "tree": "d82c9a0112a338c5a348ceb718a3218c6a800a8b",
  "parents": [
    "d4ee61f436bcc95c1d113e2854ec9352def29dda"
  ],
  "author": {
    "name": "Benoit Jacob",
    "email": "jacob.benoit.1@gmail.com",
    "time": "Fri Jun 05 12:20:37 2026 -0400"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Fri Jun 05 12:20:37 2026 -0400"
  },
  "message": "[Codegen][CPU] Add x86 AVX-512 VNNI 16x16x2 i8 MMA intrinsic. (#24534)\n\n`MMA_X86_AVX512VNNI_16x16x2_I32_I8_CASTI16` processes a full 16x16x2 i8\nmatmul tile, mirroring the mmt4d ukernel\u0027s hot loop. Unlike the 1x16x2 /\n16x1x2 CASTI16 variants -- one row per intrinsic, with a per-row i8-\u003ei16\nwiden + broadcast -- it consumes whole 16x2 i8 panels: one `vpmovsxbw`\nwiden per panel, 4 in-lane + 4 128-bit-block shuffles to fan the panels\nacross a 4x4 grid, then 16 `vpdpwssd`. The 16x16 accumulator uses a\nblock-interleaved `TileSwizzle` so each `vpdpwssd` accumulator is a\ncontiguous register.\n\ni8 inner_tiled matmul, 4096x4096 on Zen 4: 72.5ms -\u003e 52.9ms.\n\nProgress towards #24515.\n\n---------\n\nSigned-off-by: Benoit Jacob \u003cjacob.benoit.1@gmail.com\u003e\nCo-authored-by: Claude Opus 4.7 \u003cnoreply@anthropic.com\u003e",
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