)]}'
{
  "commit": "c484058957158b08c920a78734dce6ebb9a9bde0",
  "tree": "73e129e60e2e42333ab0deedf8011b63efc0238b",
  "parents": [
    "9b4906e7848ebca3e80bf662f31bff24cff77ae7"
  ],
  "author": {
    "name": "Nirvedh Meshram",
    "email": "96096277+nirvedhmeshram@users.noreply.github.com",
    "time": "Wed Jan 08 15:39:42 2025 -0600"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Wed Jan 08 15:39:42 2025 -0600"
  },
  "message": "[GPU] Add barriers when resolving GPUMappedForall to fix race condition (#19635)\n\nThe barriers added here can be pessimistic and we can look into\noptimizing them at a later point if needed. However, we end up with a\nrace if we dont have them.\nIn some local testing I did on a MI300 GPU, I did not find any\nsignificant performance impact by these barriers. For example an\nunaligned matmul + elementwise took 47us and 48us with and without the\nbarriers respectively with TileAndFuse with padding support and the\ncorresponding default path takes 68us. The prefill stage of ToyLLAMA\ntook 325us and 324us respectively with and without barriers while the\ndefault path takes 461us.\n\nSigned-off-by: Nirvedh Meshram \u003cnirvedh@gmail.com\u003e",
  "tree_diff": [
    {
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      "old_id": "334427cfffb97281ec3a5d182f24e91a09d18131",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/Common/GPU/GPUDistributeForall.cpp",
      "new_id": "63bff764a38ebc31101e73d569b6be59a93f2887",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/Common/GPU/GPUDistributeForall.cpp"
    },
    {
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      "old_path": "compiler/src/iree/compiler/Codegen/Common/GPU/test/gpu_distribute_forall.mlir",
      "new_id": "cc6b575193b8f95d1067966f319ebcae370bee44",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/Common/GPU/test/gpu_distribute_forall.mlir"
    },
    {
      "type": "modify",
      "old_id": "f71add60f4b1a95e88eccd68450d364c5a5d4360",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/pipeline_tile_and_fuse.mlir",
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      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/pipeline_tile_and_fuse.mlir"
    }
  ]
}
