)]}'
{
  "commit": "c319c2db6034a5359f73e0e2fe66b81617707b81",
  "tree": "bba00e9bb4e6a985472f739da116253d6f8cab19",
  "parents": [
    "289b9a1ebf954be3995cc1895254d09f2623341f"
  ],
  "author": {
    "name": "Ben Vanik",
    "email": "ben.vanik@gmail.com",
    "time": "Fri Feb 24 18:18:47 2023 -0800"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Sat Feb 25 02:18:47 2023 +0000"
  },
  "message": "Adding initial dispatch instrumention support. (#12357)\n\nThis adds a few new `hal.instrument.*` ops, a pass that instruments\r\ndispatches to a basic level, LLVM CPU support, a runtime tooling flag,\r\nand a prototype tool to dump the instrument data.\r\n\r\nAt the core of this is support for a new compiler-generated function\r\n`__query_instruments` that allows modules to pass back a list of\r\nbuffers. The `--instrument_file\u003d` tooling flag will gather all buffers\r\nfrom all modules and concatenate them together into a binary file. The\r\nformat of the resulting file is defined by a chunked transport stream\r\ncontaining today just the dispatch instrumentation chunk types.\r\n\r\nDispatch instrumentation will be enabled when the\r\n`--iree-hal-instrument-dispatches\u003d` flag is set to a power-of-two buffer\r\nsize. Most programs can usually get by with 16mib while memory access\r\ninstrumentation may require 256mib or 2gib.\r\n\r\nOn the CPU side the `--iree-llvmcpu-instrument-memory-accesses\u003dtrue`\r\nflag will enable tracking every load/store from/to a memref (scalars and\r\nvectors) by address and length. This can be used to observe memory\r\naccess patterns and the addresses being accessed by particular\r\nworkgroups. We should be able to support this on other backends\r\n(definitely CUDA, but possibly with SPIR-V using relative buffer offsets\r\nor something).\r\n\r\nIn addition to tracking workgroup launches and optionally memory\r\naccesses there are also placeholders for printf-style string formatting\r\nand value probes. `hal.instrument.print` still needs conversion work in\r\neach backend and though `hal.instrument.value` works there\u0027s no nice way\r\nof inserting them today.\r\n\r\nExample commands for getting a memory access dump (16MB is pretty small\r\nfor this, 2gib is better when access tracking is enabled):\r\n```sh\r\niree-compile \\\r\n    --iree-hal-target-backends\u003dllvm-cpu \\\r\n    --iree-hal-instrument-dispatches\u003d16mib \\\r\n    --iree-llvmcpu-instrument-memory-accesses\u003dtrue \\\r\n    runtime/src/iree/runtime/testdata/simple_mul.mlir \\\r\n    -o\u003dsimple_mul_instr.vmfb\r\niree-run-module \\\r\n    --device\u003dlocal-sync \\\r\n    --module\u003dsimple_mul_instr.vmfb \\\r\n    --function\u003dsimple_mul \\\r\n    --input\u003d4xf32\u003d2 \\\r\n    --input\u003d4xf32\u003d4 \\\r\n    --instrument_file\u003dinstrument.bin\r\niree-dump-instruments instrument.bin\r\n```\r\n\r\nExpected output for a simple_mul which has 4x4096 (multiple workgroups),\r\nnote that export sources are listed as well as all sites to that export\r\n(in this case just one):\r\n```\r\n$ ../iree-build/tools/iree-dump-instruments instrument_mem.bin\r\n\r\n//\u003d\u003d\u003d----------------------------------------------------------------------\u003d\u003d\u003d//\r\n// export[0]: simple_mul_dispatch_0_generic_16384\r\n//\u003d\u003d\u003d----------------------------------------------------------------------\u003d\u003d\u003d//\r\nfunc.func @simple_mul_dispatch_0_generic_16384(%arg0: !stream.binding {stream.alignment \u003d 64 : index}, %arg1: !stream.binding {stream.alignment \u003d 64 : index}, %arg2: !stream.binding {stream.alignment \u003d 64 : index}) {\r\n  %c0 \u003d arith.constant 0 : index\r\n  %0 \u003d stream.binding.subspan %arg0[%c0] : !stream.binding -\u003e !flow.dispatch.tensor\u003creadonly:tensor\u003c16384xf32\u003e\u003e\r\n  %1 \u003d stream.binding.subspan %arg1[%c0] : !stream.binding -\u003e !flow.dispatch.tensor\u003creadonly:tensor\u003c16384xf32\u003e\u003e\r\n  %2 \u003d stream.binding.subspan %arg2[%c0] : !stream.binding -\u003e !flow.dispatch.tensor\u003cwriteonly:tensor\u003c16384xf32\u003e\u003e\r\n  %3 \u003d flow.dispatch.tensor.load %0, offsets \u003d [0], sizes \u003d [16384], strides \u003d [1] : !flow.dispatch.tensor\u003creadonly:tensor\u003c16384xf32\u003e\u003e -\u003e tensor\u003c16384xf32\u003e\r\n  %4 \u003d flow.dispatch.tensor.load %1, offsets \u003d [0], sizes \u003d [16384], strides \u003d [1] : !flow.dispatch.tensor\u003creadonly:tensor\u003c16384xf32\u003e\u003e -\u003e tensor\u003c16384xf32\u003e\r\n  %5 \u003d tensor.empty() : tensor\u003c16384xf32\u003e\r\n  %6 \u003d linalg.generic {indexing_maps \u003d [affine_map\u003c(d0) -\u003e (d0)\u003e, affine_map\u003c(d0) -\u003e (d0)\u003e, affine_map\u003c(d0) -\u003e (d0)\u003e], iterator_types \u003d [\"parallel\"]} ins(%3, %4 : tensor\u003c16384xf32\u003e, tensor\u003c16384xf32\u003e) outs(%5 : tensor\u003c16384xf32\u003e) {\r\n  ^bb0(%in: f32, %in_0: f32, %out: f32):\r\n    %7 \u003d arith.mulf %in, %in_0 : f32\r\n    linalg.yield %7 : f32\r\n  } -\u003e tensor\u003c16384xf32\u003e\r\n  flow.dispatch.tensor.store %6, %2, offsets \u003d [0], sizes \u003d [16384], strides \u003d [1] : tensor\u003c16384xf32\u003e -\u003e !flow.dispatch.tensor\u003cwriteonly:tensor\u003c16384xf32\u003e\u003e\r\n  return\r\n}\r\n\r\n//\u003d\u003d\u003d----------------------------------------------------------------------\u003d\u003d\u003d//\r\n// dispatch site 0: simple_mul_dispatch_0_generic_16384\r\n//\u003d\u003d\u003d----------------------------------------------------------------------\u003d\u003d\u003d//\r\n\r\n0000000000000000 | WORKGROUP dispatch(0 simple_mul_dispatch_0_generic_16384 4x1x1) 0,0,0 pid:52\r\n0000000000000000 | LOAD  000002705bc3ad80 16\r\n0000000000000000 | LOAD  000002705bc4ae80 16\r\n0000000000000000 | STORE 000002705bc7a100 16\r\n0000000000000000 | LOAD  000002705bc3ad90 16\r\n0000000000000000 | LOAD  000002705bc4ae90 16\r\n0000000000000000 | STORE 000002705bc7a110 16\r\n0000000000000000 | LOAD  000002705bc3ada0 16\r\n0000000000000000 | LOAD  000002705bc4aea0 16\r\n0000000000000000 | STORE 000002705bc7a120 16\r\n0000000000000000 | LOAD  000002705bc3adb0 16\r\n0000000000000000 | LOAD  000002705bc4aeb0 16\r\n0000000000000000 | STORE 000002705bc7a130 16\r\n0000000000000000 | LOAD  000002705bc3adc0 16\r\n0000000000000000 | LOAD  000002705bc4aec0 16\r\n0000000000000000 | STORE 000002705bc7a140 16\r\n...\r\n000000000000c040 | WORKGROUP dispatch(0 simple_mul_dispatch_0_generic_16384 4x1x1) 1,0,0 pid:52\r\n000000000000c040 | LOAD  000002705bc3ed80 16\r\n000000000000c040 | LOAD  000002705bc4ee80 16\r\n000000000000c040 | STORE 000002705bc7e100 16\r\n...\r\n```\r\n\r\nThe printed data is currently just a proof of concept - the first column\r\nis the workgroup key - more advanced visualizations can do better things\r\n(still WIP, showing a dispatch listing and memory accesses by a\r\nparticular dispatch):\r\n\r\n![image](https://user-images.githubusercontent.com/75337/221122437-2eb50c30-f8af-415e-90cd-f67ae7fdbdcd.png)\r\n\r\n![image](https://user-images.githubusercontent.com/75337/221122967-bf37cf44-4991-484e-b654-a0b267ce527f.png)\r\n\r\n![image](https://user-images.githubusercontent.com/75337/221122600-767b7a1b-4f60-45f0-8a88-1c504d36c063.png)\r\n\r\nThere\u0027s still some iteration needed on printing values. For now a simple\r\ntest with this:\r\n```diff\r\ndiff --git a/compiler/src/iree/compiler/Codegen/LLVMCPU/ConvertToLLVM.cpp b/compiler/src/iree/compiler/Codegen/LLVMCPU/ConvertToLLVM.cpp\r\nindex 55bab04a8..24abf2255 100644\r\n--- a/compiler/src/iree/compiler/Codegen/LLVMCPU/ConvertToLLVM.cpp\r\n+++ b/compiler/src/iree/compiler/Codegen/LLVMCPU/ConvertToLLVM.cpp\r\n@@ -442,6 +442,22 @@ struct ConvertHALInstrumentWorkgroupOp\r\n             rewriter.create\u003cLLVM::ConstantOp\u003e(loc, i64Type, 0xFFFFFFFFFFll)),\r\n         rewriter.create\u003cLLVM::ConstantOp\u003e(loc, i64Type, 24));\r\n\r\n+    // HACK: test writing out a value.\r\n+    {\r\n+      Value valueOperand \u003d rewriter.create\u003carith::ConstantOp\u003e(\r\n+          loc, rewriter.getUI32IntegerAttr(0xFFFFFFFFu));\r\n+      rewriter.create\u003cIREE::HAL::InstrumentValueOp\u003e(\r\n+          loc, valueOperand.getType(), instrumentOp.getBuffer(), workgroupKey,\r\n+          rewriter.getI8IntegerAttr(0), valueOperand);\r\n+    }\r\n+    {\r\n+      Value valueOperand \u003d rewriter.create\u003carith::ConstantOp\u003e(\r\n+          loc, rewriter.getF32FloatAttr(1.234f));\r\n+      rewriter.create\u003cIREE::HAL::InstrumentValueOp\u003e(\r\n+          loc, valueOperand.getType(), instrumentOp.getBuffer(), workgroupKey,\r\n+          rewriter.getI8IntegerAttr(1), valueOperand);\r\n+    }\r\n+\r\n     rewriter.replaceOp(instrumentOp, workgroupKey);\r\n     return success();\r\n   }\r\n```\r\nwill produce this output:\r\n```\r\n0000000000000000 | WORKGROUP dispatch(0 simple_mul_dispatch_0_generic_16384 4x1x1) 0,0,0 pid:50\r\n0000000000000000 | VALUE 0000 \u003d 4294967295\r\n0000000000000000 | VALUE 0001 \u003d 1.234000e+00 1.234000\r\n0000000000000040 | WORKGROUP dispatch(0 simple_mul_dispatch_0_generic_16384 4x1x1) 1,0,0 pid:50\r\n0000000000000040 | VALUE 0000 \u003d 4294967295\r\n0000000000000040 | VALUE 0001 \u003d 1.234000e+00 1.234000\r\n0000000000000080 | WORKGROUP dispatch(0 simple_mul_dispatch_0_generic_16384 4x1x1) 2,0,0 pid:50\r\n0000000000000080 | VALUE 0000 \u003d 4294967295\r\n0000000000000080 | VALUE 0001 \u003d 1.234000e+00 1.234000\r\n00000000000000C0 | WORKGROUP dispatch(0 simple_mul_dispatch_0_generic_16384 4x1x1) 3,0,0 pid:50\r\n00000000000000C0 | VALUE 0000 \u003d 4294967295\r\n00000000000000C0 | VALUE 0001 \u003d 1.234000e+00 1.234000\r\n```\r\n\r\nErgonomics-wise for things like the value instrumentation we could try\r\nadding dialect attributes or something earlier on that tracks values or\r\nflagged patterns/etc for particular experiments.\r\n\r\nIn the future we can add both additional dispatch instrumentation and\r\nnew chunk types from various modules. Examples include\r\ncompiler-generated profile-guided optimization markers, VM code coverage\r\nmarkers, HAL counters for allocations or submissions, or device\r\ntimestamp streams.\r\n\r\nOnly the CPU backend is supported right now as that\u0027s what I\u0027m familiar\r\nwith. I\u0027d hoped to do the `hal.instrument.*` op lowering to memrefs so\r\nit could be shared but memref descriptors are unfortunately still a\r\nthing and with something tracking every single memory access it created\r\nhundreds of thousands of instructions. I eagerly await the day when\r\nsomeone works to kill memref descriptors.",
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