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{
  "commit": "bc908fd620d7378d1e2da0bff6ee70d77a965110",
  "tree": "71a7b03495dca7b586d8a2bd8a7f56ced1cee637",
  "parents": [
    "e53a335559976a31ed23225480a1baff823d2888"
  ],
  "author": {
    "name": "Zmicier Prybysh",
    "email": "zprybysh@baylibre.com",
    "time": "Wed Jul 22 14:07:17 2026 +0200"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Wed Jul 22 12:07:17 2026 +0000"
  },
  "message": "[LLVMCPU][RISCV] Add RVV bf16 mmt4d ukernel using the Zvfbfwma widening MAC (bf16*bf16-\u003ef32) (#24695)\n\n## Summary\n\nOn RISC-V, a data-tiled bf16 matmul was computed by promoting LHS/RHS to\nf32, ignoring the `Zvfbfwma` bf16 widening multiply-accumulate extension\n(`vfwmaccbf16`) that LLVM already lowers to and that shipping silicon\nimplements. This PR adds a native `bf16 x bf16 -\u003e f32` `mmt4d`\nmicrokernel for RVV+`Zvfbfwma`. Naturally, this change is related to\n(and was implementing looking at) the existing f32, `int8` (#23734), and\nf16/`Zvfh` (#22231) ukernels.\n\n## How the change was tested\n\n1. Compiler e2e\nA `128x256 bf16 * 256x128 bf16 -\u003e 128x128 f32` matmul compiled for\n`riscv64 +v,+zvfbfwma` with `--iree-opt-data-tiling\n--iree-llvmcpu-enable-ukernels\u003dall`:\n   Before: dispatch contains `arith.extf` f32-promotion, no ukernel.\nAfter: `Mmt4dTilingExpert` dispatch `matmul_128x128x256_bf16xbf16xf32`\nwith `iree_uk_mmt4d` + `iree_uk_pack`; **zero `arith.extf`**; all four\n`iree_uk_mmt4d_tile_bf16bf16f32_*_riscv_64_zvfbfwma` symbols present;\ngenerated RISC-V asm inner loop is `vfwmaccbf16.vf`.\n2. Numerics under `qemu-riscv64`\nA standalone harness calling the real tile functions matches an f32\nreference exactly. A control run without the extension crashes,\nconfirming `vfwmaccbf16` is genuinely executed. I used qemu 8.2 which\nexposes the extension as the experimental `-cpu max,x-zvfbfwma\u003dtrue`\nproperty.\n3. Tile selection under `qemu-riscv64`.\nVerified `iree_uk_mmt4d_select_tile_func_arch` (the\n`entry_point.c`/`tiles.inl` wiring) returns the correct bf16 tile for\neach M0 value when `cpu_data` has the `Zvfbfwma` bit, and does not\nselect it when the bit is clear — i.e. the feature is only enabled for\n`Zvfbfwma`.\n4. In-tree `mmt4d_test`.\nThe added case exercises the same path in CI\u0027s RISC-V cross-build (falls\nback to the generic tile if the CI toolchain can\u0027t assemble `Zvfbfwma`,\ni think it\u0027s the same limitation as `Zvfh` in #22303).\n\n### A note on CI coverage\n\nIf I understand correctly, the RISC-V CI job runs under an older\n`qemu-riscv64` on a stock `rv64gcv` profile that doesn\u0027t expose\n`Zvfbfwma`, and `mmt4d_test` *skips* (does not fail) any case whose\nfeature the runtime CPU lacks. Zvfbfwma is only assembled/executed on a\ntoolchain + qemu new enough to support it (qemu ≥ 8.2 exposes it as the\nexperimental `x-zvfbfwma` property). My point is: a green CI does not\nmean the bf16 kernel ran in CI — the functional validation of record is\nthe local `qemu-riscv64` 8.2 numerics + tile-selection runs described\nabove.\n\nDisclosure: this change was assisted by Claude Code, but the change was\nreviewed and thoroughly tested before being submitted.\n\n---------\n\nSigned-off-by: Zmicier Prybysh \u003czprybysh@baylibre.com\u003e",
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