)]}'
{
  "commit": "b94a5a53488c55ba4f3c5bbf60efc4027166a33c",
  "tree": "ced5747caf13a2f07374297e0c3def27957a1da9",
  "parents": [
    "4cf1a7cd7e5a15140c1e7679d784dd75923a2bc9"
  ],
  "author": {
    "name": "Ege Beysel",
    "email": "beysel@roofline.ai",
    "time": "Mon Jul 20 14:15:24 2026 +0200"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Mon Jul 20 14:15:24 2026 +0200"
  },
  "message": "[DT][CPU]: RVV scalable encoding materialization (#24600)\n\nThis PR introduces scalable data-tiled layout selection and\nmaterialization for RVV. Though since there exist microkernels for the\nRV64 backend with the V extension, previous mechanism to select these\ndata-tiled layouts _statically_ based on the `+zvl*b` flags is also\npreserved and the scalable data-tiled layout materialization is hidden\nbehind the flag scalable vectorization flag.\n\nThe exactl layout selection (the tile sizes) though is based on the same\nprinciples as the static one - fully utilize all 32 of the V registers.\nF16 tile sizes that underutilize the V registers in the static case (see\n[this discord\nthread](https://discord.com/channels/689900678990135345/1456679894812590326/1461764521403224209))).\n\n**NOTE**: the `+zvl*b` flags DO NOT give us the _exact_ values of VLEN\nthat the hardware implements but rather the minimum one, meaning that\nthe previous static mechanism can underutilize the vector registers and\nis not vector-length agnostic.\n\n---------\n\nSigned-off-by: Ege Beysel \u003cbeyselege@gmail.com\u003e",
  "tree_diff": [
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}