)]}'
{
  "commit": "b8aec7a1140d2a2019efec9ae7e2de7641865d7d",
  "tree": "50311b4b648942646745af099f25441ed52094a7",
  "parents": [
    "6846c286a64c047e6bc2817226ebc7e0b47739cb"
  ],
  "author": {
    "name": "Han-Chung Wang",
    "email": "hanhan0912@gmail.com",
    "time": "Mon May 11 15:46:09 2026 -0700"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Mon May 11 15:46:09 2026 -0700"
  },
  "message": "[Codegen][GPU] Avoid generic TileAndFuse promotion for convolutions. (#24435)\n\nGeneric TileAndFuse promotion can attach promote_operands to convolution\nops that did not go through a convolution-specific MMA config path.\nThose paths are responsible for selecting an MMA schedule and attaching\nmma_kind.\n\nSkip generic contraction promotion for convolution ops so direct conv\nand IGEMM configs remain the only promoted convolution paths.\n\nThis fixes NaN issues for ResNet ONNX models.\n\nFixes https://github.com/iree-org/iree/issues/24414\n\n---------\n\nSigned-off-by: hanhanW \u003chanhan0912@gmail.com\u003e",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "151f5422a1aa5dc128dcebfa547b2029a4102d13",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/Dialect/GPU/TargetUtils/ConfigUtils.cpp",
      "new_id": "fba5c36b222e9e2ab9d109420613e0e73756b7f8",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/Dialect/GPU/TargetUtils/ConfigUtils.cpp"
    },
    {
      "type": "modify",
      "old_id": "541a9b4e3872f17f750d65efda2400e2cee7a5d4",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/BUILD.bazel",
      "new_id": "5fd7192d8bd605ed796bc93cefd6016ef7fd7722",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/BUILD.bazel"
    },
    {
      "type": "modify",
      "old_id": "7086d09901104de70855e028ee13c89d8211384e",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/CMakeLists.txt",
      "new_id": "38171f6fa8d2559f3b3ddc7aa56e2b398b3d3b83",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/CMakeLists.txt"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "e3b1301321d326cfce0e152fe17252ef9a140a7c",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/config_tile_and_fuse_convolution.mlir"
    },
    {
      "type": "modify",
      "old_id": "f57f6f353c8980085eb439af3f7869e3d0638411",
      "old_mode": 33188,
      "old_path": "tests/external/iree-test-suites/onnx_models/onnx_models_gpu_hip_rdna3.json",
      "new_id": "ce93a0b37bf20564ba3c1e9374f8537c9ee5f33a",
      "new_mode": 33188,
      "new_path": "tests/external/iree-test-suites/onnx_models/onnx_models_gpu_hip_rdna3.json"
    },
    {
      "type": "modify",
      "old_id": "db32204323c7452da5406667c3f8b6507f7fbf92",
      "old_mode": 33188,
      "old_path": "tests/external/iree-test-suites/onnx_models/onnx_models_gpu_hip_rdna4.json",
      "new_id": "982b771e41f64cc3701ef90bc54dd3ae6f47bbed",
      "new_mode": 33188,
      "new_path": "tests/external/iree-test-suites/onnx_models/onnx_models_gpu_hip_rdna4.json"
    }
  ]
}