tree 10d2eefc803e9fcd7167f31ba6490362d5dac7e8
parent c1c962b63cd248f1c7b6d9a9ac8288a57d711c46
author Agustin Nahuel Coppari Hollmann <70057799+copparihollmann@users.noreply.github.com> 1780907080 -0700
committer GitHub <noreply@github.com> 1780907080 +0200
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[LLVMCPU][RISCV] Add RVV int8 vector-contract custom kernels for widening i8*i8->i32 matmul (#23734)

Fixes iree-org/iree#23730

This PR adds RVV custom vector-contract kernel support for widening
i8*i8->i32 matmul on RISC-V.

It updates:
- CPU encoding tile enumeration for RVV int8->i32 matmul
- LLVMCPU kernel dispatch RVV vector sizes
- VectorContractCustomKernels with an RVV intrinsic-based int8 path
- lit tests for vector-contract custom kernels and mmt4d vector lowering

Something I would like some feedback on is what would be your preferred
way to test this e2e. So far I compile it and run it on the Banana-pi
SpacemiT X60.

Assisted-by: ChatGPT

---------

Signed-off-by: Agustin N. Coppari Hollmann <copparihollmann@gmail.com>