)]}'
{
  "commit": "a9e91ecb68b23241349acfbb2ede00afa4c107b7",
  "tree": "2184ecf847f3902e0b389ccd909d5216de49dfa3",
  "parents": [
    "b32ca40857b9e91ed99f91ba86a730a1feb9ff49"
  ],
  "author": {
    "name": "WMC",
    "email": "tnwilly@gmail.com",
    "time": "Tue Jun 09 14:35:50 2026 +0800"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Tue Jun 09 08:35:50 2026 +0200"
  },
  "message": "[LLVMGPU] Add sm_120 TileAndFuse config coverage, consolidate MMA sync pipeline tests (#24577)\n\n## Description\nAdds LLVMGPU TileAndFuse config-selection coverage for the CUDA `sm_120`\ntarget and consolidates MMA sync pipeline-lowering coverage across\nNVIDIA\nGPU architectures.\n\nThe `sm_120` config-selection test verifies that f16 matmul cases select\nthe\nNVIDIA MMA TileAndFuse path before any architecture-specific tuning is\nintroduced. The pipeline-lowering tests are kept target-independent\nbecause\nthey start from IR with an attached `mma_sync` intrinsic and only verify\nthat\nthe selected lowering pipeline generates the corresponding\n`nvgpu.mma.sync`\nops.\n\nCovered `sm_120` config-selection cases:\n- `f16xf16 -\u003e f32` matmul selects TileAndFuse with `NV_MMA_SYNC`\n- `f16xf16 -\u003e f16` matmul selects TileAndFuse with `NV_MMA_SYNC`\n- `f16xf16 -\u003e f32` matmul accumulate sets `convert_acc_gemm`\n\nCovered target-independent pipeline-lowering cases:\n- `f16xf16 -\u003e f32` TileAndFuse lowering generates `nvgpu.mma.sync`\n- `f16xf16 -\u003e f16` TileAndFuse lowering generates `nvgpu.mma.sync`\n- `f16xf16 -\u003e f32` VectorDistribute lowering generates `nvgpu.mma.sync`\n- `f16xf16 -\u003e f16` VectorDistribute lowering generates `nvgpu.mma.sync`\n\nThis is baseline regression coverage only; it does not introduce new\ntile\nheuristics or `sm_120`-specific tuning.\n\n## Test\n- `llvm-lit -v \\\n\ncompiler/src/iree/compiler/Codegen/LLVMGPU/test/NVVM/config_tile_and_fuse_sm120.mlir\n\\\n\ncompiler/src/iree/compiler/Codegen/LLVMGPU/test/NVVM/config_tile_and_fuse_sm80.mlir\n\\\n\ncompiler/src/iree/compiler/Codegen/LLVMGPU/test/NVVM/pipeline_tile_and_fuse_mma_sync.mlir\n\\\n\ncompiler/src/iree/compiler/Codegen/LLVMGPU/test/NVVM/pipeline_vector_distribute_mma_sync.mlir`\n\n\n```\n-- Testing: 4 tests, 4 workers --\nPASS: IREE :: src/iree/compiler/Codegen/LLVMGPU/test/NVVM/config_tile_and_fuse_sm120.mlir (1 of 4)\nPASS: IREE :: src/iree/compiler/Codegen/LLVMGPU/test/NVVM/config_tile_and_fuse_sm80.mlir (2 of 4)\nPASS: IREE :: src/iree/compiler/Codegen/LLVMGPU/test/NVVM/pipeline_vector_distribute_mma_sync.mlir (3 of 4)\nPASS: IREE :: src/iree/compiler/Codegen/LLVMGPU/test/NVVM/pipeline_tile_and_fuse_mma_sync.mlir (4 of 4)\n\nTesting Time: 0.14s\n\nTotal Discovered Tests: 4\n  Passed: 4 (100.00%)\n```\n\n---------\n\nSigned-off-by: weimin023 \u003ctnwilly@gmail.com\u003e",
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