)]}'
{
  "commit": "a4d0287253fbe7211f545cda304b487218c2a711",
  "tree": "ed15bd28cc2de4925e76a46dd3e72d6fb7c0bd1f",
  "parents": [
    "540008c4aa3f6a2c6e55a054a33f24bd85144d97"
  ],
  "author": {
    "name": "WMC",
    "email": "tnwilly@gmail.com",
    "time": "Tue Jun 30 19:35:33 2026 +0800"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Tue Jun 30 13:35:33 2026 +0200"
  },
  "message": "[CUDA][LLVMGPU] Fix sm_120 WGP params and add BF16 mma.sync coverage (#24648)\n\n## Description\n\nFixes a correctness issue in `getSM120WgpDetails()` carried over from\nthe Ampere placeholder, consolidates BF16 test coverage into existing\narchitecture-scoped files, and extends sm_120 tests with a\nmixed-precision case.\n\n- **BF16 mma.sync fix**: `NV_MMA_SYNC_F32_16x8x16_BF16` was missing from\nsm_120\u0027s `mmaOps` despite being supported from Ampere onwards. sm_121\nalready advertises this intrinsic. Without this fix, bf16 × bf16 → f32\nmatmuls silently fall back to SIMT tiling on sm_120.\n\n- **Test consolidation**: Per the reviewer\u0027s suggestion, tests no longer\nhave their own per-architecture files. Instead they are folded into the\nexisting architecture-scoped test files.\n\n## Testcases\n\n1. config_tile_and_fuse_sm80.mlir / config_tile_and_fuse_sm120.mlir:\neach gets a new BF16 section verifying that bf16 × bf16 → f32 selects\n`NV_MMA_SYNC_F32_16x8x16_BF16` at the config stage.\n\n1. config_tile_and_fuse_sm120.mlir: adds a mixed-precision f32 × bf16 →\nf32 case to verify the SIMT fallback path when no MMA intrinsic matches\nthe operand types.\n\n1. pipeline_tile_and_fuse_mma_sync.mlir: adds a shared BF16 pipeline\nlowering section that covers both sm_80 and sm_120, verifying\n`nvgpu.mma.sync` is generated with the correct shape.\n\n1. target_device_features.mlir: expands the SM120 metadata check to a\nfull wgp attribute check (mma list, workgroup sizes, memory limits),\nmatching the granularity of the existing SM89 check.\n\n1. bf16_mma_sm80.mlir: deleted — coverage moved into the files above.\n\n---------\n\nSigned-off-by: weimin023 \u003ctnwilly@gmail.com\u003e",
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