)]}'
{
  "commit": "a0465a3d7dc13eb471c35ca401070988a521595f",
  "tree": "c2aa2f49ea3eda48677894758f4e29a89e757bc8",
  "parents": [
    "16396e421e8a58e0a95bb406f17683aefe699cee"
  ],
  "author": {
    "name": "Pooja Hemashekar",
    "email": "hemashekar@roofline.ai",
    "time": "Mon Jul 27 10:19:48 2026 +0200"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Mon Jul 27 10:19:48 2026 +0200"
  },
  "message": "[Runtime] Add initial data-tiled conv ukernel (generic \u0026 avx512) (#24729)\n\nAdds a data-tiled convolution microkernel with a generic implementation\nand an avx512 optimized tile kernel with inner tile sizes (OW_TILE\u003d16,\nK0\u003d16, C0\u003d16).\n\nLayouts (c0 \u003d inner IC block, k0 \u003d inner OC block):\n    input [N, IC/c0, H, W, c0]\n    filter [OC/k0, IC/c0, FH, FW, c0, k0]\n    output [N, OC/k0, OH, OW, k0]\n\nThe ABI uses explicit outer-dimension strides. These strides refer to\nthe full parent tensor layout rather than the extracted slab, ensuring\ncorrect addressing when kernels operate on subviews of the tensor. Only\nthe inner W/c0/k0 dims are contiguous.\n\nScope: f32 only; dilation\u003d1 (dilated convs are not matched by the\ndispatch); requires the packed NCHWc layout, with the arch path selected\nonly for k0\u003dc0\u003d16. Additional types and tile shapes are future work.\n\n---------\n\nSigned-off-by: Pooja Hemashekar \u003chemashekar@roofline.ai\u003e",
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