[Codegen][CPU] Flatten contiguous trailing dims of transfers before unrolling. (#24517) `VectorTransferLoweringPass` applies the MLIR transfer-lowering patterns with `maxTransferRank=1` plus full-unroll, which fully unrolls any rank-N>1 `vector.transfer_read`/`transfer_write` to multiple rank-1 transfers (one per index of the outer dim). For multi-dim tiles whose trailing dims are contiguous in memory, this unrolls a single wide load into many narrow ones, which then have to be reassembled into a wide vector via a chain of `shufflevector`s in the hot inner loop. Example surfacing the cost: a 4096x4096 dynamic-shape bf16xbf16->f32 matmul with `--iree-llvmcpu-enable-inner-tiled` on Zen 4 lowered to inner_tiled with N=16, K_inner=2. The RHS for one K-step is a `vector<16x2xbf16>` from a contiguous 64-byte slice. Unrolling to 16 separate `<2 x bfloat>` loads forced a sequence of `vpermt2d`/ `vpermt2q` per K-iteration in the inner loop to rebuild the wide RHS register — accounting for ~3 cycles of extra work per K-step on top of the 29 dpbf16ps doing the real work. Apply `populateFlattenVectorTransferPatterns` *before* the rank-reduction patterns. It rewrites a multi-dim transfer with contiguous trailing dims into a transfer on a `memref.collapse_shape` view + a `vector.shape_cast`, so the read ends up as a single 1-D transfer over the collapsed view and lowers to one wide `vector.load`. Per-fragment effect on the matmul benchmark above: 80.8 ms -> 67.1 ms (1.20x). Combined with the m_bcst-fold broadcast routing in a sibling commit, end-to-end gets to 53.4 ms (within 5% of the precompiled mmt4d ukernel at 50.9 ms). Test fallout: two pipelines now lower a per-row pack-tile load into a single wide load over a collapsed-memref view rather than one load per row (`aligned_unpack_generic` in pipeline_pack_unpack_tests) / write a constant `vector<4x2xi1>` mask as a single flat `vector<8xi1>` store (`transpose_mask` in vector_lowering). The new IR is strictly fewer ops in both cases; updated the CHECK lines to match. Progress towards #24515. --------- Signed-off-by: Benoit Jacob <jacob.benoit.1@gmail.com> Co-authored-by: Claude Opus 4.7 <noreply@anthropic.com>
IREE (Intermediate Representation Execution Environment, pronounced as “eerie”) is an MLIR-based end-to-end compiler and runtime that lowers Machine Learning (ML) models to a unified IR that scales up to meet the needs of the datacenter and down to satisfy the constraints and special considerations of mobile and edge deployments.
See our website for project details, user guides, and instructions on building from source.
Releases notes are published on GitHub releases.
| Package | Release status |
|---|---|
| GitHub release (stable) | |
| GitHub release (nightly) | |
iree-base-compiler | |
iree-base-runtime |
For more details on the release process, see https://iree.dev/developers/general/release-management/.
| Operating system | Build status |
|---|---|
| Linux | |
| macOS | |
| macOS |
For the full list of workflows see https://iree.dev/developers/general/github-actions/.
See our website for more information.
Community meeting recordings: IREE YouTube channel
| Date | Title | Recording | Slides |
|---|---|---|---|
| 2025-06-10 | Data-Tiling in IREE: Achieving High Performance Through Compiler Design (AsiaLLVM) | recording | slides |
| 2025-05-17 | Introduction to GPU architecture and IREE's GPU CodeGen Pipeline | recording | slides |
| 2025-02-12 | The Long Tail of AI: SPIR-V in IREE and MLIR (Vulkanised) | recording | slides |
| 2024-10-01 | Unveiling the Inner Workings of IREE: An MLIR-Based Compiler for Diverse Hardware | recording | |
| 2021-06-09 | IREE Runtime Design Tech Talk | recording | slides |
| 2020-08-20 | IREE CodeGen (MLIR Open Design Meeting) | recording | slides |
| 2020-03-18 | Interactive HAL IR Walkthrough | recording | |
| 2020-01-31 | End-to-end MLIR Workflow in IREE (MLIR Open Design Meeting) | recording | slides |
IREE is licensed under the terms of the Apache 2.0 License with LLVM Exceptions. See LICENSE for more information.