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{
  "commit": "9d485fc23e8ddec4cdf24923ce2e71a47fce8915",
  "tree": "7d9fcd89aacca7f0b4d74d5b4b5596d26bf82a82",
  "parents": [
    "0492b214495cda17591a865027fb331a32da1fe9"
  ],
  "author": {
    "name": "Pooja Hemashekar",
    "email": "hemashekar@roofline.ai",
    "time": "Wed Sep 02 14:45:26 2026 +0200"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Wed Sep 02 14:45:26 2026 +0200"
  },
  "message": "[CI] Add bare-metal RISCV 64 sample and QEMU smoke test (#24844)\n\nAdds `samples/baremetal_riscv64`, a single-op inference runner for\nbare-metal RISCV 64 under `qemu-system-riscv64` (`-machine virt`, no OS,\nsemihosted I/O), together with a pkgci smoke test.\n\nThe sample covers two execution paths:\n- `llvm-cpu` using `inline-dynamic` and the embedded-ELF loader.\n- `vmvx-inline` using `inline-static`.\n\nThe runner uses the inline HAL instead of the full-HAL implementation\nfollowing `samples/simple_embedding`, because HAL device creation\ncurrently requires a proactor that `IREE_PLATFORM_GENERIC` does not\nprovide.\n\nThe runtime is compiled and linked using an xPack GCC/newlib sysroot.\nIts newlib is built with `-mcmodel\u003dmedany` required for QEMUs RAM base\nand provides `semihost.specs` for semihosted I/O and exit handling.\n\nNo HAL device drivers are enabled; the embedded-ELF loader is enabled\nexplicitly for the LLVMCPU runner. The sample is `EXCLUDE_FROM_ALL` and\nCI builds only `samples/baremetal_riscv64/all`, so it does not affect\nother Generic RISCV builds.\n\n\nAssisted-by: Claude Code\n\nSigned-off-by: Pooja Hemashekar \u003chemashekar@roofline.ai\u003e",
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