)]}'
{
  "commit": "9bb6fe01f1d2759a0c223184a45d93cec4108481",
  "tree": "2f639f56ca2966f677a42fa8fbc0947a281e426a",
  "parents": [
    "80a3c85474aafaacb8a2e2c6faf698e9c63154c6"
  ],
  "author": {
    "name": "MaheshRavishankar",
    "email": "1663364+MaheshRavishankar@users.noreply.github.com",
    "time": "Tue Nov 02 10:09:29 2021 -0700"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Tue Nov 02 10:09:29 2021 -0700"
  },
  "message": "Initial commit of bridge to use Linalg Comprehensive Bufferize Pass. (#7509)\n\nCo-authored-by: Nicolas Vasilache \u003cnicolasvasilache@users.noreply.github.com\u003e\r\n\r\nThis is the initial commit to use Linalg Comprehensive bufferize pass\r\nfrom within IREE. The main work here is to bridge the memory model gap\r\nof using flow.dispatch.tensor.load/store operations.",
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