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{
  "commit": "9acea6ac572f30a28b19c70118d94b4457f87420",
  "tree": "bbfca14ec489b75bcfa68ef56a2220323bf595c7",
  "parents": [
    "54eeda625b3894b13239591fc2f8a5ffb6b2bf2f"
  ],
  "author": {
    "name": "Jakub Kuderski",
    "email": "jakub@nod-labs.com",
    "time": "Fri Sep 11 19:22:28 2026 -0400"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Fri Sep 11 23:22:28 2026 +0000"
  },
  "message": "[ROCM] Name gfx1250 CDNA5 and add MI455X target details (#24923)\n\nAMD published the CDNA5 architecture and MI455X specifications a few\nweeks ago:\nhttps://www.amd.com/content/dam/amd/en/documents/products/technologies/cdna/amd-cdna5-whitepaper.pdf\n\nMove the existing gfx1250 WGP definition alongside the other CDNA\nfamilies and add cdna5 and mi455x target aliases. Populate the MI455X\nchip definition with the published WGP count, memory bandwidth, and peak\ncompute rates. Document the confirmed WGP limits and update the\narchitecture naming in compiler and runtime documentation.\n\nNormalize SKU and architecture aliases before forming executable target\nIDs for the amdgpu device. Without this, mi455x and cdna5 are emitted as\nexecutable formats that the runtime cannot match, even though the\nembedded target_info already names gfx1250.\n\nAdd coverage for target metadata, Wave32 serialization, and canonical\nAMDGPU executable formats with feature suffixes.\n\nAssisted-by: codex (gpt-6-astra)",
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