)]}'
{
  "commit": "8cc05f517efb04e4302e8e35e73ed598f9dc234f",
  "tree": "8e0b28e6469a6c8310ad2d7e8fc975d823bdf527",
  "parents": [
    "16191ce4a0e641e5212ec0aef75600ce3c8b60c8"
  ],
  "author": {
    "name": "Han-Chung Wang",
    "email": "hanhan0912@gmail.com",
    "time": "Thu May 07 16:51:41 2026 -0700"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Thu May 07 16:51:41 2026 -0700"
  },
  "message": "[CPU] Improve tiling config for elementwise ops with dynamic shapes. (#24383)\n\nThe default distribution tile sizes were 64s for dynamic shape, which\nalso requires a fixup in elementwise ops. Otherwise, the runtime\noverheads dominates the performance. We identified the issue for static\ncases before, and the recent study also points out that it is needed for\ndynamic shapes. See https://github.com/iree-org/iree/issues/24012 for\nmore details.\n\nNote that it is not common in full model workload because they are\nmostly fused with producers, so it was not on our radar until today.\n\nSigned-off-by: hanhanW \u003chanhan0912@gmail.com\u003e",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "133dac2d5e00e26765b00a1f2d3dfe9ce5ebd872",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp",
      "new_id": "5f22ca3349e1bff3d99ec9657872e4c4895b6fc0",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp"
    },
    {
      "type": "modify",
      "old_id": "ae83e9892b27814d10a0c090b666eeda3b5e359d",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/select_x86_64_lowering_strategy.mlir",
      "new_id": "65a612917e00842ea36a27b66a7c3a351b7acb06",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/select_x86_64_lowering_strategy.mlir"
    }
  ]
}