)]}'
{
  "commit": "85efc86b545ba8173de2e88f4293c7bbfb4fc941",
  "tree": "405479f6eb3bcf7d1841aa3926bc3d995d0f1b09",
  "parents": [
    "1b177e95689e8e5a9102a379c532d6d625f75a4a"
  ],
  "author": {
    "name": "Benjamin Maxwell",
    "email": "benjamin.maxwell@arm.com",
    "time": "Wed Oct 25 20:15:14 2023 +0100"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Wed Oct 25 20:15:14 2023 +0100"
  },
  "message": "[CPU][SVE] Enforce \u003e 1 pow2 sizes when materializing scalable matmul lowering_configs (#15276)\n\nThe backend struggles to legalize non-power-of-two scalable vector sizes\r\nand in many cases aborts. So if we can avoid it, we should stick to\r\npower-of-two sizes. Likewise, 1x scalable vectors (e.g. vector\u003c[1]xty\u003e)\r\nare poorly supported, so we fallback to fixed vectorization in that\r\ncase.",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "a48b4703e25384b7a53936dbbb8e8b4363b3b5d7",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp",
      "new_id": "84d86497763cabde9bfa78b5e401d627509285df",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp"
    },
    {
      "type": "modify",
      "old_id": "f3fa65457ef1a14a76e5150785ac104bc2992f8b",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/materialize_aarch64_launch_configuration.mlir",
      "new_id": "ff4cff5b7debf6facfe5bfa0f28cc4c8b90ace05",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/materialize_aarch64_launch_configuration.mlir"
    }
  ]
}