[Stream] Bounds-check tied operand index in verifyTiedOperandEncodings (#24686)
## Summary
Bounds-check the tied-operand index in `verifyTiedOperandEncodings` so
an out-of-range `tied_operands` value is reported as a verification
error instead of indexing the operand-encodings array out of bounds.
## Context
`verifyTiedOperandEncodings` (used by tied stream ops such as
`stream.tensor.dispatch`) walks each result's tied operand and compares
`operandEncodings[operandIndex]` against the result encoding.
`operandIndex` is derived from the op's `tied_operands` attribute.
## Problem
The `tied_operands` value is not range-checked for this op before the
encoding lookup, so an index beyond the operand count reads
`operandEncodings` out of bounds. Such an index is reachable through the
generic assembly form (which bypasses the op's custom-format checks) —
for example, a dispatch with a single operand encoding but a
`tied_operands` entry pointing at operand 5:
```mlir
%0 = "stream.tensor.dispatch"(...) {
tied_operands = array<i64: 5>, ...
} : (...) -> ...
```
`operandIndex` (5) then indexes the single-element `operandEncodings`
out of bounds during verification.
## Fix
If `operandIndex >= operandEncodings.size()`, emit a verification error
(`tied operand index N is out of range of the M operand encoding(s)`)
instead of indexing out of bounds.
---
Disclosure: this contribution was authored with an AI coding assistant
(Claude) and reviewed before submission.
---------
Signed-off-by: Eylon Krause <eylon1909@gmail.com>IREE (Intermediate Representation Execution Environment, pronounced as “eerie”) is an MLIR-based end-to-end compiler and runtime that lowers Machine Learning (ML) models to a unified IR that scales up to meet the needs of the datacenter and down to satisfy the constraints and special considerations of mobile and edge deployments.
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| Date | Title | Recording | Slides |
|---|---|---|---|
| 2025-06-10 | Data-Tiling in IREE: Achieving High Performance Through Compiler Design (AsiaLLVM) | recording | slides |
| 2025-05-17 | Introduction to GPU architecture and IREE's GPU CodeGen Pipeline | recording | slides |
| 2025-02-12 | The Long Tail of AI: SPIR-V in IREE and MLIR (Vulkanised) | recording | slides |
| 2024-10-01 | Unveiling the Inner Workings of IREE: An MLIR-Based Compiler for Diverse Hardware | recording | |
| 2021-06-09 | IREE Runtime Design Tech Talk | recording | slides |
| 2020-08-20 | IREE CodeGen (MLIR Open Design Meeting) | recording | slides |
| 2020-03-18 | Interactive HAL IR Walkthrough | recording | |
| 2020-01-31 | End-to-end MLIR Workflow in IREE (MLIR Open Design Meeting) | recording | slides |
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