Integrates/llvm 20240621 (#17723)
Bump stablehlo to:
https://github.com/openxla/stablehlo/commit/57d16b101fb8b71bee13fa93e320d0cccef87f52
Bump llvm-project to:
https://github.com/llvm/llvm-project/commit/c83d9e99b0663cf8e7e81bd552d42a0c4298ab2c
diff --git a/compiler/plugins/input/StableHLO/Conversion/test/stablehlo_to_linalg_ext.mlir b/compiler/plugins/input/StableHLO/Conversion/test/stablehlo_to_linalg_ext.mlir
index 38792b3..917f2f8 100644
--- a/compiler/plugins/input/StableHLO/Conversion/test/stablehlo_to_linalg_ext.mlir
+++ b/compiler/plugins/input/StableHLO/Conversion/test/stablehlo_to_linalg_ext.mlir
@@ -377,8 +377,8 @@
// CHECK: %[[ARG0:[a-zA-Z0-9]+]]
// CHECK: %[[ARG1:[a-zA-Z0-9]+]]
// CHECK: %[[ARG2:[a-zA-Z0-9]+]]
-// CHECK: %[[BITCAST0:.+]] = builtin.unrealized_conversion_cast %[[ARG0]] : tensor<1xui32> to tensor<1xi32>
-// CHECK: %[[BITCAST2:.+]] = builtin.unrealized_conversion_cast %[[ARG2]] : tensor<1xui32> to tensor<1xi32>
+// CHECK-DAG: %[[BITCAST0:.+]] = builtin.unrealized_conversion_cast %[[ARG0]] : tensor<1xui32> to tensor<1xi32>
+// CHECK-DAG: %[[BITCAST2:.+]] = builtin.unrealized_conversion_cast %[[ARG2]] : tensor<1xui32> to tensor<1xi32>
// CHECK: %[[SCATTER:.+]] = iree_linalg_ext.scatter
// CHECK-SAME: unique_indices(true)
// CHECK-SAME: ins(%[[BITCAST2]], %[[ARG1]] : tensor<1xi32>, tensor<1x1xi32>)
diff --git a/compiler/src/iree/compiler/Codegen/Common/test/convert_bf16_arith_to_f32.mlir b/compiler/src/iree/compiler/Codegen/Common/test/convert_bf16_arith_to_f32.mlir
index aa3e3bb..c588805 100644
--- a/compiler/src/iree/compiler/Codegen/Common/test/convert_bf16_arith_to_f32.mlir
+++ b/compiler/src/iree/compiler/Codegen/Common/test/convert_bf16_arith_to_f32.mlir
@@ -28,8 +28,8 @@
// CHECK-LABEL: @addf_bf16
// CHECK-SAME: %[[ARG0:.+]]: bf16,
// CHECK-SAME: %[[ARG1:.+]]: bf16
-// CHECK: %[[EXT0:.+]] = arith.extf %[[ARG0]] : bf16 to f32
-// CHECK: %[[EXT1:.+]] = arith.extf %[[ARG1]] : bf16 to f32
+// CHECK-DAG: %[[EXT0:.+]] = arith.extf %[[ARG0]] : bf16 to f32
+// CHECK-DAG: %[[EXT1:.+]] = arith.extf %[[ARG1]] : bf16 to f32
// CHECK: %[[ADD:.+]] = arith.addf %[[EXT0]], %[[EXT1]] : f32
// CHECK: %[[TRUNC:.+]] = arith.truncf %[[ADD]] : f32 to bf16
@@ -43,8 +43,8 @@
// CHECK-LABEL: @addf_vector_bf16
// CHECK-SAME: %[[ARG0:.+]]: vector<4xbf16>,
// CHECK-SAME: %[[ARG1:.+]]: vector<4xbf16>
-// CHECK: %[[EXT0:.+]] = arith.extf %[[ARG0]] : vector<4xbf16> to vector<4xf32>
-// CHECK: %[[EXT1:.+]] = arith.extf %[[ARG1]] : vector<4xbf16> to vector<4xf32>
+// CHECK-DAG: %[[EXT0:.+]] = arith.extf %[[ARG0]] : vector<4xbf16> to vector<4xf32>
+// CHECK-DAG: %[[EXT1:.+]] = arith.extf %[[ARG1]] : vector<4xbf16> to vector<4xf32>
// CHECK: %[[ADD:.+]] = arith.addf %[[EXT0]], %[[EXT1]] : vector<4xf32>
// CHECK: %[[TRUNC:.+]] = arith.truncf %[[ADD]] : vector<4xf32> to vector<4xbf16>
@@ -107,17 +107,17 @@
}
// CHECK-LABEL: @store_reduction_bf16
-// CHECK: %[[CST:.+]] = arith.constant dense<1.000000e+00> : vector<bf16>
-// CHECK: %[[VAL0:.+]] = arith.extf %arg0 : vector<3xbf16> to vector<3xf32>
-// CHECK: %[[VAL1:.+]] = arith.extf %arg1 : vector<3xbf16> to vector<3xf32>
-// CHECK: %[[VAL2:.+]] = vector.extractelement %[[CST]][] : vector<bf16>
-// CHECK: %[[VAL3:.+]] = arith.extf %[[VAL2]] : bf16 to f32
-// CHECK: %[[VAL4:.+]] = arith.mulf %[[VAL0]], %[[VAL1]] : vector<3xf32>
-// CHECK: %[[VAL5:.+]] = vector.reduction <add>, %[[VAL4]], %[[VAL3]] : vector<3xf32> into f32
-// CHECK: %[[VAL6:.+]] = arith.truncf %[[VAL5]] : f32 to bf16
-// CHECK: %[[VAL7:.+]] = vector.broadcast %[[VAL6]] : bf16 to vector<bf16>
-// CHECK: %[[VAL8:.+]] = vector.extractelement %[[VAL7]][] : vector<bf16>
-// CHECK: memref.store %[[VAL8]], %arg2[] : memref<bf16>
+// CHECK: %[[CST:.+]] = arith.constant dense<1.000000e+00> : vector<bf16>
+// CHECK-DAG: %[[VAL0:.+]] = arith.extf %arg0 : vector<3xbf16> to vector<3xf32>
+// CHECK-DAG: %[[VAL1:.+]] = arith.extf %arg1 : vector<3xbf16> to vector<3xf32>
+// CHECK: %[[VAL2:.+]] = vector.extractelement %[[CST]][] : vector<bf16>
+// CHECK: %[[VAL3:.+]] = arith.extf %[[VAL2]] : bf16 to f32
+// CHECK: %[[VAL4:.+]] = arith.mulf %[[VAL0]], %[[VAL1]] : vector<3xf32>
+// CHECK: %[[VAL5:.+]] = vector.reduction <add>, %[[VAL4]], %[[VAL3]] : vector<3xf32> into f32
+// CHECK: %[[VAL6:.+]] = arith.truncf %[[VAL5]] : f32 to bf16
+// CHECK: %[[VAL7:.+]] = vector.broadcast %[[VAL6]] : bf16 to vector<bf16>
+// CHECK: %[[VAL8:.+]] = vector.extractelement %[[VAL7]][] : vector<bf16>
+// CHECK: memref.store %[[VAL8]], %arg2[] : memref<bf16>
// -----
diff --git a/compiler/src/iree/compiler/Codegen/Dialect/GPU/Transforms/Transforms.cpp b/compiler/src/iree/compiler/Codegen/Dialect/GPU/Transforms/Transforms.cpp
index fb529d6..14b62d7 100644
--- a/compiler/src/iree/compiler/Codegen/Dialect/GPU/Transforms/Transforms.cpp
+++ b/compiler/src/iree/compiler/Codegen/Dialect/GPU/Transforms/Transforms.cpp
@@ -797,7 +797,7 @@
Location loc = forallOp->getLoc();
assert(isLaneMappableForall(forallOp) && "mapping non-lane forall op");
- Value laneId = rewriter.create<gpu::LaneIdOp>(loc);
+ Value laneId = rewriter.create<gpu::LaneIdOp>(loc, /*upperBound=*/nullptr);
rewriter.eraseOp(forallOp.getTerminator());
rewriter.setInsertionPoint(forallOp);
rewriter.inlineBlockBefore(forallOp.getBody(), forallOp, {laneId});
diff --git a/compiler/src/iree/compiler/Codegen/WGSL/WGSLReplacePushConstants.cpp b/compiler/src/iree/compiler/Codegen/WGSL/WGSLReplacePushConstants.cpp
index c757d46..fefb4a5 100644
--- a/compiler/src/iree/compiler/Codegen/WGSL/WGSLReplacePushConstants.cpp
+++ b/compiler/src/iree/compiler/Codegen/WGSL/WGSLReplacePushConstants.cpp
@@ -53,9 +53,9 @@
// AnyFloat
Value resizedValue = extractElementOp.getResult();
if (sourceBitWidth > destBitWidth) {
- return builder.create<arith::TruncFOp>(loc, opType, extractElementOp);
+ return builder.create<arith::TruncFOp>(loc, opType, resizedValue);
} else if (sourceBitWidth < destBitWidth) {
- return builder.create<arith::ExtFOp>(loc, opType, extractElementOp);
+ return builder.create<arith::ExtFOp>(loc, opType, resizedValue);
}
return builder.create<arith::BitcastOp>(loc, opType, resizedValue);
}
diff --git a/third_party/llvm-project b/third_party/llvm-project
index 144ebdd..c83d9e9 160000
--- a/third_party/llvm-project
+++ b/third_party/llvm-project
@@ -1 +1 @@
-Subproject commit 144ebdd07a9872580ffcbd55147826882ccb0768
+Subproject commit c83d9e99b0663cf8e7e81bd552d42a0c4298ab2c
diff --git a/third_party/stablehlo b/third_party/stablehlo
index dd48ec5..57d16b1 160000
--- a/third_party/stablehlo
+++ b/third_party/stablehlo
@@ -1 +1 @@
-Subproject commit dd48ec58d3bb8d674adf56715d4394102538fa84
+Subproject commit 57d16b101fb8b71bee13fa93e320d0cccef87f52
