commit | 7497689acb7125046625bc78dfb43dc7da9eff38 | [log] [tgz] |
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author | Manish Gupta <manigupta@google.com> | Wed Mar 15 14:37:15 2023 -0700 |
committer | GitHub <noreply@github.com> | Wed Mar 15 14:37:15 2023 -0700 |
tree | 7b1ba381138601b3825b86324ec866eb89f35070 | |
parent | 62ee2f342484a1468abe5bc96a2be7c3192a6e63 [diff] |
Mainloop multistaged pipeline and instruction scheduling for NVIDIA Ampere Tensor Cores (F16 and F32) (#12603) This PR creates a coarse-grained multistage pipelining and fine-grained instruction scheduling for optimal performance on NVIDIA Ampere Tensor Cores. Multi-staging is essential to hide the Global Memory load latency by building longer software pipelines and using the available Shared Memory capacity, especially on NVIDIA A100. Additionally, fine-grained instruction scheduling hides the Shared Memory load latency by prefetching the math operands into registers. The PR adds support for F16 and F32 datatype using `mma.sync` native Tensor Core exposure.
IREE (Intermediate Representation Execution Environment, pronounced as “eerie”) is an MLIR-based end-to-end compiler and runtime that lowers Machine Learning (ML) models to a unified IR that scales up to meet the needs of the datacenter and down to satisfy the constraints and special considerations of mobile and edge deployments.
See our website for project details, user guides, and instructions on building from source.
IREE is still in its early phase. We have settled down on the overarching infrastructure and are actively improving various software components as well as project logistics. It is still quite far from ready for everyday use and is made available without any support at the moment. With that said, we welcome any kind of feedback on any communication channels!
See our website for more information.
IREE is licensed under the terms of the Apache 2.0 License with LLVM Exceptions. See LICENSE for more information.