)]}'
{
  "commit": "597629e7b3bccd8ffce6e542e3230d0c5bc84e16",
  "tree": "1730a9717d320193ca1117b97ada14496913cbc3",
  "parents": [
    "98ddf0c9c524082762d7c93182ccd63d36e31aec"
  ],
  "author": {
    "name": "Lukas Sommer",
    "email": "lukas.sommer@amd.com",
    "time": "Fri May 08 09:07:59 2026 +0200"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Fri May 08 09:07:59 2026 +0200"
  },
  "message": "[Codegen] Limit async scope in pipelining (#24350)\n\nCurrently, the pipelining assumes that all `amdgpu.gather_to_lds`\noperations are part of the loop that is being pipelined and marks them\nas async, with waits inserted in the pipelined loop.\n\nThis assumption was fine for the workloads so far, but with work\nunderway to enable pipelining for attention, this no longer holds, as\nthe load of e.g. the `Q` matrix can be outside of the loop. Operations\noutside the loop can also be marked async, but that requires inserting\nmarks and waits before the loop.\n\nThis PR fixes this by recording a marker in the block before the loop\nand later on inserting marks and waits for async operations before the\nmarker.\n\nThis is part of https://github.com/iree-org/iree/issues/23782.\n\nAssisted-by: Claude Code and Codex\n\n---------\n\nSigned-off-by: Lukas Sommer \u003clukas.sommer@amd.com\u003e",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "eb4d47bda9d119e5f3793ff2967b053db4bc8416",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMGPU/Utils/ROCDLPrefetchSharedMemoryCopy.cpp",
      "new_id": "b1ad15838e26e0ea362c9dde47b758fecbc2437d",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMGPU/Utils/ROCDLPrefetchSharedMemoryCopy.cpp"
    },
    {
      "type": "modify",
      "old_id": "019c0ab986a2cf5da854fae30f4c032ed65f508a",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMGPU/test/prefetch_shared_memory.mlir",
      "new_id": "bda838fdc2a2fb0630758cc0e35ca997b7eaeef9",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMGPU/test/prefetch_shared_memory.mlir"
    }
  ]
}