[Metal] Fix indirect dispatch offset for sub-allocated parameter buffers (#24644)

iree_hal_metal_command_buffer_prepare_dispatch resolved the
indirect-dispatch workgroup-count buffer offset as just
config.workgroup_count_ref.offset, dropping
iree_hal_buffer_byte_offset(buffer) -- the base offset of the parameter
buffer within its backing allocation. This is inconsistent with the
sibling descriptor path in the same function (which adds byte_offset)
and with every other backend: Vulkan and amdgpu route all offsets
through a shared resolver that adds byte_offset, and the local HAL
resolves through iree_hal_buffer_map_range. When the indirect-parameter
buffer is a sub-allocation with a non-zero base offset, the dispatch
read the three workgroup-count uint32s from the wrong address and ran a
wrong grid.

The bug was latent because the Metal allocator returns standalone root
buffers (byte_offset==0) and the cross-backend CTS indirect-parameters
tests allocate the parameter buffer directly at offset 0.

Add byte_offset so the source offset matches the descriptor path and the
other backends:
workgroups_offset =
iree_hal_buffer_byte_offset(config.workgroup_count_ref.buffer) +
config.workgroup_count_ref.offset;

Adds CTS regression test
DispatchIndirectParametersTest.SubAllocatedParameterBuffer, which
references the workgroup counts through an iree_hal_buffer_subspan at a
non-zero base offset (placing deliberately-wrong counts at offset 0 so a
base-offset drop reads a deterministic grid instead of garbage). This is
the only test shape that catches the bug, and it exercises it on every
backend that supports sub-allocated buffers (Metal, Vulkan, amdgpu).

Signed-off-by: Alex Vasile
<48962821+Alex-Vasile@users.noreply.github.com>

Signed-off-by: Alex Vasile <48962821+Alex-Vasile@users.noreply.github.com>
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README.md

IREE: Intermediate Representation Execution Environment

IREE (Intermediate Representation Execution Environment, pronounced as “eerie”) is an MLIR-based end-to-end compiler and runtime that lowers Machine Learning (ML) models to a unified IR that scales up to meet the needs of the datacenter and down to satisfy the constraints and special considerations of mobile and edge deployments.

See our website for project details, user guides, and instructions on building from source.

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Community meeting recordings: IREE YouTube channel

DateTitleRecordingSlides
2025-06-10Data-Tiling in IREE: Achieving High Performance Through Compiler Design (AsiaLLVM)recordingslides
2025-05-17Introduction to GPU architecture and IREE's GPU CodeGen Pipelinerecordingslides
2025-02-12The Long Tail of AI: SPIR-V in IREE and MLIR (Vulkanised)recordingslides
2024-10-01Unveiling the Inner Workings of IREE: An MLIR-Based Compiler for Diverse Hardwarerecording
2021-06-09IREE Runtime Design Tech Talkrecordingslides
2020-08-20IREE CodeGen (MLIR Open Design Meeting)recordingslides
2020-03-18Interactive HAL IR Walkthroughrecording
2020-01-31End-to-end MLIR Workflow in IREE (MLIR Open Design Meeting)recordingslides

License

IREE is licensed under the terms of the Apache 2.0 License with LLVM Exceptions. See LICENSE for more information.